Pressure detecting device and method for manufacturing the same, display device and method for manufacturing the same, and tft substrate with pressure detecting device

ABSTRACT

A pressure detecting device includes a glass substrate as a substrate, a lower electrode arranged on the glass substrate, an upper electrode spaced apart from the lower electrode and facing the lower electrode, the upper electrode having holes as one or more through-openings, and a source line as a change extracting wiring for detecting a change in electrical state caused by the upper electrode receiving pressure to deflect toward the lower electrode.

TECHNICAL FIELD

The present invention relates to a pressure detecting device and a method for manufacturing the same, a display device and a method for manufacturing the same, and a TFT substrate with a pressure detecting device.

BACKGROUND ART

A pressure sensor having a structure in which electrodes in the shape of flat plate are spaced apart from and face each other in the vertical direction with a gap left therebetween can be considered as one form of pressure sensor. In order to produce such a pressure sensor, a stack of sandwich structure in which a sacrificial layer is formed on a conductive layer which is to be a lower electrode and a conductive layer which is to be an upper electrode is further formed thereon is prepared. It can be considered to inject an etching solution through a side surface at which the sacrificial layer is directly exposed in this stack to etch the sacrificial layer. However, this etching is etching that removes the sacrificial layer but does not remove the upper and lower electrodes. After the whole sacrificial layer is removed by this etching, a structure in which the upper and lower electrodes are spaced apart from and face each other with a gap left therebetween is obtained.

Japanese Patent Laying-Open No. 2003-106915 (PTL 1) discloses a pressure sensor for sensing a fingerprint, for example. In order to obtain this pressure sensor, in PTL 1, a structure in which a first metal layer of Mo, an intermediate layer of Al and a second metal layer of Mo are stacked sequentially on a substrate and the second metal layer is further covered with an insulating protection film is produced first. In this structure, a hole is made in the protection film and the second metal layer, so that the intermediate layer is exposed at this hole. In PTL 1, an etching solution shall be injected via this hole to etch the intermediate layer. The hole through which the intermediate layer is exposed is limited in size whereas a region where the intermediate layer is desired to be removed spreads out two-dimensionally. Thus, typically, enormous time is required for removing the whole intermediate layer, or the intermediate layer cannot be fully removed. However, in PTL 1 in which the first and second metal layers are formed of Mo and the intermediate layer is formed of Al, Al of the intermediate layer shall be removable in a short time utilizing a battery effect between Mo and Al. With the technique described in PTL 1, after removing the intermediate layer, a structure in which the first and second metal layers are spaced apart from and face each other with a gap left therebetween is obtained.

CITATION LIST Patent Literature

-   PTL 1: Japanese Patent Laying-Open No. 2003-106915

SUMMARY OF INVENTION Technical Problem

Although it may be possible to efficiently remove the intermediate layer made of Al, the technique described in PTL 1, which is based on utilizing the galvanic action between dissimilar metals, is premised on that the upper and lower layers intended to face each other with a gap left therebetween are both metal layers and are directly exposed to the gap in the structure targeted for production. Therefore, use of the technique described in PTL 1 is limited to the case of producing such a structure. For example, the technique described in PTL 1 cannot handle a case where it is required to produce a structure in which an electrode is not directly exposed but covered with an insulating layer on either the upper or lower side as viewed from the gap.

Therefore, the present invention has an object to provide a pressure detecting device and a method for manufacturing the same that can efficiently form a gap irrespective of whether upper and lower layers directly exposed to the gap are metal layers when manufacturing a pressure sensor having a structure in which electrodes in the shape of flat plate are spaced apart from and face each other in the vertical direction with the gap left therebetween, a display device and a method for manufacturing the same, and a TFT substrate with a pressure detecting device.

Solution to Problem

In order to achieve the above-described object, a pressure detecting device based on the present invention includes a substrate, a lower electrode arranged on the substrate, an upper electrode spaced apart from the lower electrode and facing the lower electrode, the upper electrode having one or more through-openings, and a change extracting wiring for detecting a change in electrical state caused by the upper electrode receiving pressure to deflect toward the lower electrode.

Advantageous Effects of Invention

According to the present invention, since the upper electrode facing the lower electrode has one or more through-openings, a gap can be efficiently formed by distributing an etching solution via these through-openings at the time of manufacture.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram schematically showing a circuit diagram of a liquid crystal display device according to a first embodiment.

FIG. 2 is a plan view when a part of the liquid crystal display device is viewed two-dimensionally from the common substrate side.

FIG. 3 is a plan view of a TFT array substrate located under the common substrate.

FIG. 4 is a cross-sectional view schematically showing a cross section taken along line IV-IV in FIG. 2.

FIG. 5 is a cross-sectional view taken along line V-V shown in FIG. 2.

FIG. 6 is a cross-sectional view of the liquid crystal display device when the common substrate is pressed.

FIG. 7 is a plan view schematically showing a region where an upper electrode is in contact with an upper insulating layer 136.

FIG. 8 is a graph comparing a characteristic of a pressure sensor according to the first embodiment and a characteristic of a pressure sensor according to a comparative example.

FIG. 9 is a cross-sectional view showing a display device including the pressure sensor according to the comparative example.

FIG. 10 is a cross-sectional view showing a first step of a process of manufacturing the TFT array substrate.

FIG. 11 is a cross-sectional view showing a second step of the process of manufacturing the TFT array substrate.

FIG. 12 is a cross-sectional view showing a third step of the process of manufacturing the TFT array substrate.

FIG. 13 is a cross-sectional view showing a fourth step of the process of manufacturing the TFT array substrate.

FIG. 14 is a cross-sectional view showing a fifth step of the process of manufacturing the TFT array substrate.

FIG. 15 is a cross-sectional view showing a sixth step of the process of manufacturing the TFT array substrate.

FIG. 16 is a cross-sectional view showing a seventh step of the process of manufacturing the TFT array substrate.

FIG. 17 is a cross-sectional view showing a first step of a process of manufacturing the common substrate.

FIG. 18 is a cross-sectional view showing a second step of the process of manufacturing the common substrate.

FIG. 19 is a cross-sectional view showing a third step of the process of manufacturing the common substrate.

FIG. 20 is a cross-sectional view showing a fourth step of the process of manufacturing the common substrate.

FIG. 21 is a cross-sectional view showing a fifth step of the process of manufacturing the common substrate.

FIG. 22 is a cross-sectional view of a liquid crystal display device according to a second embodiment and is a cross-sectional view showing a TFT element.

FIG. 23 is a cross-sectional view of the liquid crystal display device according to the second embodiment and is a cross-sectional view in an output element.

FIG. 24 is a cross-sectional view showing a manufacturing step after the manufacturing step shown in FIG. 15, in a process of manufacturing a TFT array substrate of the liquid crystal display device according to the second embodiment.

FIG. 25 is a cross-sectional view showing a manufacturing step after the manufacturing step for the TFT array substrate shown in FIG. 24.

FIG. 26 is a cross-sectional view showing a manufacturing step for the TFT array substrate after the manufacturing step shown in FIG. 25.

FIG. 27 is a cross-sectional view of a liquid crystal display device according to a third embodiment and is a cross-sectional view showing a TFT element.

FIG. 28 is a cross-sectional view of the liquid crystal display device according to the third embodiment and is a cross-sectional view showing a pressure sensor.

FIG. 29 is a cross-sectional view schematically showing a state of the liquid crystal display device when a common substrate is pressed.

FIG. 30 is a cross-sectional view showing an upper electrode and a gate insulating layer before the upper electrode and the gate insulating layer are deformed by the pressing force from a pressing member.

FIG. 31 is a plan view of the upper electrode.

FIG. 32 is a cross-sectional view showing a state where the upper electrode and the gate insulating layer have been deformed by the pressing force from the pressing member.

FIG. 33 is a plan view of the upper electrode when the upper electrode has been deformed as shown in FIG. 32.

FIG. 34 is a cross-sectional view showing a first step of a process of manufacturing a TFT array substrate.

FIG. 35 is a cross-sectional view showing a second step of the process of manufacturing the TFT array substrate.

FIG. 36 is a cross-sectional view showing a third step of the process of manufacturing the TFT array substrate.

FIG. 37 is a cross-sectional view showing a modification of the TFT array substrate shown in FIG. 28.

FIG. 38 is a circuit diagram schematically showing a circuit diagram of a liquid crystal display device according to a fourth embodiment.

FIG. 39 is a cross-sectional view of the liquid crystal display device according to the fourth embodiment and is a cross-sectional view showing a TFT element.

FIG. 40 is a cross-sectional view of the liquid crystal display device according to the fourth embodiment and is a cross-sectional view showing a TFT element for selection and a pressure sensor.

FIG. 41 is a cross-sectional view schematically showing a state where a common substrate is pressed.

FIG. 42 is a cross-sectional view showing a first step of a process of manufacturing a TFT array substrate.

FIG. 43 is a cross-sectional view showing a second step of the process of manufacturing the TFT array substrate.

FIG. 44 is a cross-sectional view showing a third step of the process of manufacturing the TFT array substrate.

FIG. 45 is a cross-sectional view showing a first step of a process of manufacturing the common substrate.

FIG. 46 is a cross-sectional view showing a second step of the process of manufacturing the common substrate.

FIG. 47 is a cross-sectional view showing a third step of the process of manufacturing the common substrate.

FIG. 48 is a cross-sectional view showing a fourth step of the process of manufacturing the common substrate.

FIG. 49 is a cross-sectional view showing a fifth step of the process of manufacturing the common substrate.

FIG. 50 is a cross-sectional view of a liquid crystal display device according to a fifth embodiment and is a cross-sectional view showing a TFT element.

FIG. 51 is a cross-sectional view of the liquid crystal display device and is a cross-sectional view showing a TFT element for selection and a pressure sensor.

FIG. 52 is a cross-sectional view showing a step when the TFT element and the TFT element for selection are formed, in a process of manufacturing a TFT array substrate.

FIG. 53 is a cross-sectional view showing a manufacturing step for the TFT array substrate after the manufacturing step shown in FIG. 52.

FIG. 54 is a cross-sectional view showing a manufacturing step after the manufacturing step shown in FIG. 53.

FIG. 55 is a cross-sectional view showing formation of a color filter substrate in a process of manufacturing a common substrate.

FIG. 56 is a cross-sectional view showing a step after the manufacturing step shown in FIG. 55.

FIG. 57 is a cross-sectional view showing a step after the manufacturing step shown in FIG. 56.

FIG. 58 is a circuit diagram showing an electrical circuit of a liquid crystal display device according to a sixth embodiment.

FIG. 59 is a cross-sectional view of the liquid crystal display device according to the sixth embodiment and is a cross-sectional view showing a TFT element.

FIG. 60 is a cross-sectional view of the liquid crystal display device according to the sixth embodiment and is a cross-sectional view showing a pressure sensor.

FIG. 61 is a cross-sectional view showing an upper electrode and a semiconductor layer in a state (initial state) where a common substrate is not pressed.

FIG. 62 is a plan view of the upper electrode.

FIG. 63 is a cross-sectional view showing the upper electrode and the semiconductor layer in the state where the common substrate has been pressed.

FIG. 64 is a cross-sectional view showing a first step of a process of manufacturing a TFT array substrate.

FIG. 65 is a cross-sectional view showing a second step of the process of manufacturing the TFT array substrate.

FIG. 66 is a cross-sectional view showing a third step of the process of manufacturing the TFT array substrate.

FIG. 67 is a cross-sectional view showing a fourth step of the process of manufacturing the TFT array substrate.

FIG. 68 is a cross-sectional view showing a fifth step of the process of manufacturing the TFT array substrate.

FIG. 69 is a cross-sectional view showing a sixth step of the process of manufacturing the TFT array substrate.

FIG. 70 is a cross-sectional view showing a seventh step of the process of manufacturing the TFT array substrate.

FIG. 71 is a cross-sectional view showing an eighth step of the process of manufacturing the TFT array substrate.

FIG. 72 is a cross-sectional view showing a ninth step of the process of manufacturing the TFT array substrate.

FIG. 73 is a cross-sectional view showing a tenth step of the process of manufacturing the TFT array substrate.

FIG. 74 is a cross-sectional view showing an eleventh step of the process of manufacturing the TFT array substrate.

FIG. 75 is a cross-sectional view of a liquid crystal display device according to a seventh embodiment and is a cross-sectional view showing a TFT element.

FIG. 76 is a cross-sectional view of the liquid crystal display device according to the seventh embodiment and is a cross-sectional view showing a pressure sensor.

FIG. 77 is a cross-sectional view showing a first step of a process of manufacturing a TFT array substrate.

FIG. 78 is a cross-sectional view showing a second step of the process of manufacturing the TFT array substrate.

FIG. 79 is a cross-sectional view showing a third step of the process of manufacturing the TFT array substrate.

FIG. 80 is a cross-sectional view showing a fourth step of the process of manufacturing the TFT array substrate.

FIG. 81 is a cross-sectional view showing a modification of the liquid crystal display device according to the seventh embodiment.

FIG. 82 is a cross-sectional view showing a pressure detecting device according to an eighth embodiment based on the present invention.

FIG. 83 is a cross-sectional view of the pressure detecting device according to the eighth embodiment based on the present invention with a pressure being applied.

FIG. 84 is a cross-sectional view showing a modification of the pressure detecting device according to the eighth embodiment based on the present invention.

FIG. 85 is a cross-sectional view of a pressure sensor included in the pressure detecting device according to the eighth embodiment based on the present invention.

FIG. 86 is a cross-sectional view of a pressure sensor included in a pressure detecting device according to a ninth embodiment based on the present invention.

FIG. 87 is a cross-sectional view of a modification of the pressure sensor included in the pressure detecting device according to the ninth embodiment based on the present invention.

FIG. 88 is a flowchart of a method for manufacturing a pressure detecting device according to a tenth embodiment based on the present invention.

FIG. 89 is a cross-sectional view of a structure obtained by a preferable example of the method for manufacturing the pressure detecting device according to the tenth embodiment based on the present invention.

DESCRIPTION OF EMBODIMENTS

When the number, an amount or the like is mentioned in the embodiments described below, the scope of the present invention is not necessarily limited to that number, that amount or the like, unless otherwise specified. In addition, in the embodiments below, each component is not necessarily essential in the present invention, unless otherwise specified. Moreover, when a plurality of embodiments are shown below, combination as appropriate of features in the embodiments is originally encompassed, unless otherwise specified.

(Pressure Sensor)

First, in order to clarify the basic idea of a pressure detecting device, detailed structures of a pressure sensor, application examples to a display device and methods for manufacturing the same will be described as the first to seventh embodiments with reference to FIGS. 1 to 81. Pressure sensors suitable for application of the present invention are those that will be described in the third, sixth and seventh embodiments. The first, second, fourth, and fifth embodiments relate to reference techniques. The present invention will be described further in the eighth and subsequent embodiments.

Although the first to seventh embodiments will be described assuming a display device with a touch panel function mainly to be a liquid crystal display device, the type of display device that the display device with a touch panel function has is not limited to a liquid crystal display device.

First Embodiment

FIG. 1 is a circuit diagram schematically showing a circuit diagram of a liquid crystal display device 100 according to a first embodiment as a reference technique. As shown in this FIG. 1, liquid crystal display device 100 includes a control unit 105 and a plurality of pixels 110 arranged in an array. Pixel 110 includes a plurality of TFT (Thin Film Transistor) elements 115 and a pixel electrode 114 connected to this TFT element 115.

Liquid crystal display device 100 includes a plurality of gate lines 112 and gate lines for sensing 113 extending in a first direction and spaced apart from one another in a second direction, and a plurality of source lines 111 extending in the second direction and spaced apart from one another in the first direction.

Each gate line 112 is connected to a gate driver 102, and each source line 111 is connected to a source driver 101. Gate line for sensing 113 is arranged between adjacent gate lines 112, and the plurality of gate lines for sensing 113 extend in the first direction and are spaced apart from one another in the second direction. Each gate line for sensing 113 is connected to a sensor driver 103.

Source driver 101, gate driver 102 and sensor driver 103 are connected to control unit 105. Two adjacent gate lines 112 and two adjacent source lines 111 define pixel 110.

TFT element 115, a TFT element for selection 116 and a pressure sensing element 120 are arranged in pixel 110. A source electrode of TFT element 115 is connected to source line 111, and a gate electrode of TFT element 115 is connected to gate line 112. Pixel electrode 114 is connected to a drain electrode of TFT element 115.

A source electrode of TFT element for selection 116 is connected to source line 111, and a gate electrode of TFT element for selection 116 is connected to gate line for sensing 113. Pressure sensing element 120 is connected to a drain electrode of TFT element for selection 116.

Pressure sensing element 120 includes an output element 117 connected to the drain electrode of TFT element for selection 116, and a pressure sensor (pressure detecting device) 118 connected to a gate electrode of this output element 117. Output element 117 includes a source electrode connected to the drain electrode of TFT element for selection 116, a drain electrode connected to source line 111, and the gate electrode connected to a lower electrode of pressure sensor 118. Source line 111 to which the source electrode of TFT element for selection 116 is connected is another source line 111 that is adjacent to source line 111 to which the drain electrode of output element 117 is connected.

ON/OFF of TFT element for selection 116 is switched as appropriate in a time division, and control unit 105 senses an output from pressure sensing element 120 connected to selected TFT element for selection 116. Specifically, control unit 105 senses an amount of current, which is an electrical characteristic from pressure sensing element 120.

An output of output element 117 fluctuates in accordance with a voltage applied to the gate electrode of output element 117. This voltage applied to the gate electrode is determined by a potential of the lower electrode of pressure sensor 118 connected to the gate electrode. The potential of the lower electrode of pressure sensor 118 is determined by a capacitance between the upper electrode and the lower electrode. The capacitance between the upper electrode and the lower electrode fluctuates in accordance with the pressing force applied to the substrate having the upper electrode. In other words, control unit 105 can sense the pressing force applied to the substrate, based on the amount of current from output element 117.

FIG. 2 is a plan view when a part of liquid crystal display device 100 is viewed two-dimensionally from the common substrate 150 side. As shown in this FIG. 2, common substrate 150 includes a color filter substrate 151 and a common electrode 152 arranged on a lower surface of this color filter substrate 151.

Color filter substrate 151 includes a black matrix 155 formed in the shape of a grid, and a colored layer 153 formed within the frame of this black matrix 155 and made of red, green and blue coloring photosensitive materials. One colored layer 153 is arranged above one pixel 110.

Common electrode 152 is a transparent electrode made of, for example, ITO (Indium Tin Oxide).

FIG. 3 is a plan view of a TFT array substrate 130 located under common substrate 150. In this FIG. 3 and FIG. 2 above, source line 111 and gate line 112 are located under black matrix 155. TFT element for selection 116 and pressure sensing element 120 are arranged on the opposite side of TFT element 115 with respect to pixel electrode 114.

As shown in this FIG. 3, TFT element for selection 116 includes a semiconductor layer 123, a source electrode 121 connecting semiconductor layer 123 and source line 111, a gate electrode 122 connected to gate line for sensing 113, and a drain electrode 125.

A source electrode 183 of output element 117 and drain electrode 125 of TFT element for selection 116 are connected by a connection wiring 124. In the present embodiment, semiconductor layer 123 of TFT element for selection 116 and a semiconductor layer 180 of output element 117 are separated from each other, and drain electrode 125 of TFT element for selection 116 and source electrode 183 of output element 117 are connected by connection wiring 124. Semiconductor layer 123 may, however, be integrated with semiconductor layer 180 so as to connect drain electrode 125 and source electrode 183.

FIG. 4 is a cross-sectional view schematically showing a cross section taken along line IV-IV in FIG. 2. The cross-sectional views shown in FIG. 4 and FIGS. 5, 6 and the like below are cross-sectional views simplified for convenience of description, and the aspect ratio and the like in each figure are not accurate.

As shown in FIG. 4, liquid crystal display device 100 includes TFT array substrate 130, common substrate 150 spaced apart from TFT array substrate 130 so as to face TFT array substrate 130, and a liquid crystal layer (display medium layer) 160 filled between common substrate 150 and TFT array substrate 130. A spacer 161 maintaining a spacing between TFT array substrate 130 and common substrate 150 at a predetermined spacing is formed between TFT array substrate 130 and common substrate 150.

Liquid crystal display device 100 further includes a polarizing plate arranged on an upper surface of common substrate 150, and a polarizing plate and a backlight unit arranged on a lower surface of TFT array substrate 130.

The polarizing plates are arranged such that the polarization direction of the polarizing plate arranged on the upper surface of common substrate 150 is orthogonal to the polarization direction of the polarizing plate arranged under TFT array substrate 130. The backlight unit emits light toward TFT array substrate 130. This backlight unit and the aforementioned two polarizing plates are not shown.

Common substrate 150 includes a glass substrate 156 having a main surface, color filter substrate 151 formed on the main surface of glass substrate 156, and common electrode 152 formed under this color filter substrate 151.

TFT array substrate 130 includes a glass substrate (first substrate) 140 having a main surface (first main surface), and pixel electrode 114 located above glass substrate 140, and TFT element (switching element) 115 is formed on the main surface of this glass substrate 140.

An underlying layer 131 formed of an insulating layer such as a silicon oxide layer (SiO₂ layer), a silicon nitride layer (SiN) and a silicon oxynitride layer (SiNO layer) is formed on the main surface of glass substrate 140. This underlying layer 131 has a film thickness of, for example, 0 nm or more and 500 nm or less, and preferably 0 nm or more and 400 nm or less.

TFT element 115 includes a semiconductor layer 132 formed on an upper surface of underlying layer 131, a gate insulating layer 133 formed to cover this semiconductor layer 132, a gate electrode 134 formed on an upper surface of gate insulating layer 133, and a drain electrode 137 and a source electrode 138 connected to semiconductor layer 132.

Gate electrode 134 is located on an upper surface of gate insulating layer 133 and above semiconductor layer 132. Drain electrode 137 is spaced apart from gate electrode 134. Source electrode 138 is located on the opposite side of drain electrode 137 with respect to gate electrode 134. Source electrode 138 is connected to source line 111, and drain electrode 137 is connected to pixel electrode 114.

Application of a predetermined voltage to gate electrode 134 causes TFT element 115 to be turned on. Application of a predetermined voltage to source line 111 and source electrode 138 causes a predetermined voltage to be applied to drain electrode 137 and pixel electrode 114.

TFT element 115 switches the voltage applied to pixel electrode 114, thereby controlling the direction of liquid crystals in liquid crystal layer 160 located between pixel electrode 114 and common electrode 152. By switching the direction of the liquid crystals, a switch is made between a state where light from the backlight unit passes through the polarizing plate arranged on the upper surface of common substrate 150 and a state where light from the backlight unit is blocked by the polarizing plate arranged on the upper surface of common substrate 150.

A continuous grain silicon film or the like is, for example, used as semiconductor layer 132. Semiconductor layer 132 has a film thickness of, for example, 20 nm or more and 200 nm or less. Semiconductor layer 132 preferably has a film thickness of approximately 30 nm or more and 70 nm or less.

Gate insulating layer 133 is formed of, for example, an insulating layer made of SiO₂, SiN, SiNO and the like. Gate insulating layer 133 has a film thickness of, for example, 20 nm or more and 200 nm or less, and preferably 50 nm or more and 120 nm or less.

Gate electrode 134 is a conductive layer that is formed of, for example, a metal layer made of tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or an alloy containing these, or a compound containing an element such as tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo), or the like. Gate electrode 134 has a film thickness of, for example, 50 nm or more and 600 nm or less. Gate electrode 134 preferably has a film thickness of 100 nm or more and 500 nm or less.

An interlayer dielectric 135 is formed on the upper surface of gate insulating layer 133 to cover gate electrode 134. Interlayer dielectric 135 is formed of for example, an insulating layer made of SiO₂, SiN, SiNO and the like. Interlayer dielectric 135 has a film thickness of, for example, 100 nm or more and 1000 nm or less. Interlayer dielectric 135 preferably has a film thickness of 100 nm or more and 700 nm or less.

Source line 111 is located on an upper surface of interlayer dielectric 135, and source electrode 138 is connected to source line 111. Drain electrode 137 is also formed to reach the upper surface of interlayer dielectric 135.

Source line 111, source electrode 138 and drain electrode 137 may be, for example, a metal layer made of aluminum (Al), copper (Cu), gold (Au), titanium (Ti) and the like, or stacked metal layers formed by sequentially stacking these metal layers. These source line 111 and the like have a film thickness of, for example, 300 nm or more and 1000 nm or less. Source line 111 and the like preferably have a film thickness of 400 nm or more and 800 nm or less.

An upper insulating layer 136 is formed on the upper surface of interlayer dielectric 135 to cover source line 111. Upper insulating layer 136 is formed of an insulating layer made of SiO₂, SiN, SiNO and the like. Upper insulating layer 136 has a film thickness of, for example, 50 nm or more and 500 nm or less. Upper insulating layer 136 preferably has a film thickness of 50 nm or more and 200 nm or less.

Pixel electrode 114 is formed on an upper surface of upper insulating layer 136. Pixel electrode 114 is formed of a transparent conductive layer made of ITO and the like.

FIG. 5 is a cross-sectional view taken along line V-V shown in FIG. 2. As shown in this FIG. 5, underlying layer 131 is formed on the main surface of glass substrate 140, and output element 117 is formed on the upper surface of this underlying layer 131.

Output element 117 includes semiconductor layer 180 formed on underlying layer 131, gate insulating layer 133 formed to cover semiconductor layer 180, a gate electrode 181 formed on a portion of the upper surface of gate insulating layer 133 located above semiconductor layer 180, and source electrode 183 and a drain electrode 182 connected to semiconductor layer 180.

Source electrode 183 is spaced apart from gate electrode 181, and drain electrode 182 is arranged on the opposite side of source electrode 183 with respect to gate electrode 181.

Interlayer dielectric 135 is formed on the upper surface of gate insulating layer 133 to cover gate electrode 181.

Drain electrode 182 passes through gate insulating layer 133 and interlayer dielectric 135 and is connected to source line 111 formed on the upper surface of interlayer dielectric 135. Source electrode 183 is also formed to pass through gate insulating layer 133 and interlayer dielectric 135 and reach the upper surface of interlayer dielectric 135.

A lower electrode 172 and connection wiring 124 are formed on the upper surface of interlayer dielectric 135. Connection wiring 124 is connected to drain electrode 125 of TFT element for selection 116 shown in FIG. 3. Lower electrode 172 is connected to gate electrode 181 by a contact 184. Therefore, a voltage applied to gate electrode 181 is determined by a potential of lower electrode 172.

Upper insulating layer 136 is formed on lower electrode 172. Lower electrode 172 is formed into a flat surface. At least a portion of upper insulating layer 136 located on lower electrode 172 is formed into a flat surface to conform to an upper surface of lower electrode 172.

Pressure sensor (pressure detecting device) 118 includes aforementioned lower electrode 172 and an upper electrode 171 located above this lower electrode 172.

In the present embodiment, upper electrode 171 is formed in common substrate 150, and upper electrode 171 is constituted by a projection 170 formed on the lower side of color filter substrate 151 and common electrode 152 formed to cover a surface of this projection 170.

Projection 170 is made of, for example, an elastically deformable material such as an acrylic resin and a plastic resin. Projection 170 may be made of an elastically deformable conductive resin.

Projection 170 has a height of, for example, 1 μm or more and 10 μm or less. Projection 170 preferably has a height of 1.5 μm or more and 5 μm or less.

In the example shown in this FIG. 5, a portion of common electrode 152 located at a vertex of projection 170 is in contact with upper insulating layer 136.

In the present embodiment, projection 170 is formed to be circular in a cross section vertical to the protruding direction, and projection 170 has a smoothly curved surface. Furthermore, as shown in FIG. 2, a plurality of projections 170 are formed to be spaced apart from one another.

The shape of projection 170 is not limited to the aforementioned shape. For example, projection 170 may be formed to extend over lower electrodes 172 of a plurality of pressure sensors 118. Projection 170 is not limited to a projection having a circular cross-sectional shape, and further, is not limited to a projection having a smoothly curved outer surface.

FIG. 6 is a cross-sectional view of liquid crystal display device 100 when common substrate 150 is pressed. As shown in this FIG. 6, when common substrate 150 is pressed by a pen or someone's finger, a pressed portion and a neighboring portion of common substrate 150 deflect.

As a result of deflection of glass substrate 156, upper electrode 171 comes closer to lower electrode 172. Since upper electrode 171 comes closer to lower electrode 172, upper electrode 171 is pressed against upper insulating layer 136, projection 170 deforms elastically, and upper electrode 171 deforms to conform to lower electrode 172.

FIG. 7 is a plan view schematically showing a region where upper electrode 171 is in contact with upper insulating layer 136. In this FIG. 7, a region R1 is a region enclosed by a broken line in FIG. 7 and a region R2 is a region enclosed by a solid line. Region R1 represents a region where upper electrode 171 is in contact with upper insulating layer 136 in a state (initial state) where common substrate 150 is not pressed.

Region R2 represents a region where upper electrode 171 is in contact with upper insulating layer 136 in the state shown in FIG. 6. As shown in this FIG. 7, by slight displacement of upper electrode 171, a contact area between upper electrode 171 and upper insulating layer 136 increases greatly.

At the portion where upper electrode 171 is in contact with upper insulating layer 136, both upper electrode 171 and lower electrode 172 are in contact with upper insulating layer 136, and a spacing between upper electrode 171 and lower electrode 172 corresponds to a thickness of upper insulating layer 136.

Specifically, a distance between common electrode 152 located on a surface of upper electrode 171 and lower electrode 172 corresponds to a thickness of upper insulating layer 136.

As a result, a capacitance defined by upper electrode 171 and lower electrode 172 in the state shown in FIG. 7 is much larger than a capacitance defined by upper electrode 171 and lower electrode 172 in the initial state shown in FIG. 6.

FIG. 8 is a graph comparing a characteristic of pressure sensor 118 according to the present embodiment and a characteristic of a pressure sensor according to a comparative example.

In the graph shown in this FIG. 8, the horizontal axis indicates an amount of stroke of the upper electrode and the vertical axis indicates a capacitance change rate between the upper electrode and the lower electrode. In the graph, a solid line L1 indicates the characteristic of the pressure sensor according to the present embodiment and a broken line L2 indicates the characteristic of the pressure sensor according to the comparative example.

FIG. 9 is a cross-sectional view showing a display device including the pressure sensor according to the comparative example. Unlike pressure sensor 118 according to the present embodiment, the pressure sensor according to the comparative example shown in this FIG. 9 does not include projection 170. Therefore, the pressure sensor according to the comparative example includes common electrode 152 formed into a flat surface on the lower surface of color filter substrate 151, and lower electrode 172.

A distance between common substrate 150 in the comparative example and TFT array substrate 130 as well as a distance between common substrate 150 in the present embodiment and TFT array substrate 130 are both 3.3 μm.

In this comparative example, when common substrate 150 is pressed, common electrode 152 comes closer to lower electrode 172. Since a distance between common electrode 152 and lower electrode 172 becomes smaller, a capacitance between common electrode 152 and lower electrode 172 becomes larger.

As shown in FIG. 8 above, when an amount of displacement (amount of stroke) of the upper electrode is small, a capacitance fluctuation rate of the pressure sensor according to the comparative example is smaller than a capacitance fluctuation rate of pressure sensor 118 according to the present embodiment.

In the pressure sensor according to the comparative example, when the pressing force applied to common substrate 150 is small, it is difficult to accurately sense fluctuations in the capacitance and it is difficult to accurately sense the applied pressure.

On the other hand, as shown in FIG. 8, it can be seen that in pressure sensor 118 according to the present embodiment, the capacitance change rate is large even when the amount of stroke of the upper electrode is small. Therefore, in pressure sensor 118 according to the present embodiment, a voltage applied to gate electrode 181 shown in FIG. 5 can be fluctuated greatly even when the amount of stroke of the upper electrode is small. As a result, the control unit can accurately sense the applied pressing force.

In the pressure sensor according to the comparative example, when the amount of stroke exceeds a predetermined value, the capacitance change rate increases sharply. In a range where the capacitance changes sharply, the capacitance changes sharply even when a distance between the upper electrode and the lower electrode is reduced slightly. Therefore, in the range where the capacitance changes sharply, the voltage applied to the gate electrode of the output element also changes sharply and an amount of current from output element 117 also fluctuates greatly. Therefore, it is difficult for the control unit to calculate the accurate pressing force.

On the other hand, in pressure sensor 118 according to the present embodiment, the capacitance change rate is substantially constant even when the amount of stroke increases. As described above, in pressure sensor 118 according to the present embodiment, the capacitance change rate is substantially constant. Therefore, the applied pressure can be easily calculated based on the capacitance between the upper electrode and the lower electrode, and the applied pressure can be accurately calculated.

As described above, pressure sensor 118 according to the present embodiment includes lower electrode 172, upper electrode 171 spaced apart from this lower electrode 172 and arranged to face the lower electrode, and upper insulating layer (insulating layer) 136 formed between upper electrode 171 and lower electrode 172, and upper electrode 171 is formed on the surface of elastically deformable projection 170. Projection 170 abuts upper insulating layer 136 and further is pressed against upper insulating layer 136, and thereby common electrode 152 on projection 170 deforms to conform to lower electrode 172. The capacitance between lower electrode 172 and upper electrode 171 changes at predetermined magnitude with a certain change rate being kept. Therefore, by sensing the amount of current from output element 117, the capacitance between upper electrode 171 and lower electrode 172 can be sensed and the applied pressure can be accurately calculated.

As described above, pressure sensor 118 that can accurately output the capacitance fluctuations is mounted on liquid crystal display device 100 according to the first embodiment. Therefore, the pressing force applied to common substrate 150 can be accurately calculated even when common substrate 150 does not deflect greatly. As a result, even when glass substrate 156 of common substrate 150 is formed to be thicker than glass substrate 140, the applied pressing force can be calculated. Therefore, the rigidity of common substrate 150 can be enhanced.

Glass substrate 140 is supported by the backlight unit and the like. Therefore, even when glass substrate 140 is made thinner than glass substrate 156, defotination of TFT array substrate 130 is suppressed. The characteristic of pressure sensor 118 shown by the solid line in FIG. 8 is one example. Therefore, it is not necessary that the capacitance change rate should increase in a manner of linear function when the amount of stroke of the upper electrode increases as shown in FIG. 8. A rate of increase in the capacitance change rate may be partially different or the capacitance change rate may change in a manner of a curved line.

In FIG. 5, semiconductor layer 180 is formed on the upper surface of gate insulating layer 133 similarly to semiconductor layer 132 shown in FIG. 4. Semiconductor layer 180 is made of a material of the same kind (the same material) as that of semiconductor layer 132, and semiconductor layer 180 and semiconductor layer 132 have substantially the same film thickness. Specifically, a continuous grain silicon film or the like is, for example, used and semiconductor layer 132 has a film thickness of, for example, 20 nm or more and 200 nm or less. Semiconductor layer 132 preferably has a film thickness of approximately 30 nm or more and 70 nm or less.

Gate electrode 181 is also formed on gate insulating layer 133 similarly to gate electrode 134 shown in FIG. 4. Furthermore, gate electrode 181 is made of a material of the same kind (the same material) as that of gate electrode 134, and a film thickness of gate electrode 181 is also substantially identical to that of gate electrode 134.

A stacked metal film that is the same as drain electrode 137 and source electrode 138 shown in FIG. 4 is used as drain electrode 182, source electrode 183, lower electrode 172, and contact 184.

As described above, the structure of output element 117 is substantially the same as that of TFT element 115. Therefore, each member of output element 117 can be simultaneously formed when each member of TFT element 115 is formed. Furthermore, the lower electrode of pressure sensor 118 can also be simultaneously formed when drain electrode 137 and source electrode 138 of TFT element 115 are formed.

Therefore, the number of steps of manufacturing TFT array substrate 130 does not increase and an increase in manufacturing cost can be suppressed.

A method for manufacturing liquid crystal display device 100 according to the present embodiment will be described with reference to FIGS. 10 to 21.

When liquid crystal display device 100 is manufactured, TFT array substrate 130 and common substrate 150 are first formed independently. Thereafter, the liquid crystal layer is applied onto the upper surface of TFT array substrate 130, and then, common substrate 150 is arranged above TFT array substrate 130. TFT array substrate 130 is thus formed.

Thus, a method for manufacturing TFT array substrate 130 will be described first.

FIG. 10 is a cross-sectional view showing a first step of a process of manufacturing TFT array substrate 130. As shown in FIG. 10, glass substrate 140 is prepared. Thereafter, the insulating layer made of SiO₂, SiN, SiNO and the like is deposited on the main surface of glass substrate 140 to form underlying layer 131.

FIG. 11 is a cross-sectional view showing a second step of the process of manufacturing TFT array substrate 130. In this FIG. 11, an amorphous semiconductor layer is first formed. A material of the amorphous semiconductor film is not particularly limited as long as the conductivity thereof is semiconductive. Silicon (Si), germanium (Ge), gallium-arsenide (GaAs) and the like are used as the material of the amorphous semiconductor film, and silicon is preferable because it is inexpensive and suitable for mass production. A method for forming the amorphous semiconductor film is not particularly limited. A method for forming an amorphous silicon (a-Si) film by a CVD and the like is, for example, used as the method for forming the amorphous semiconductor film.

Thereafter, a catalytic element is added to the amorphous semiconductor layer. The catalytic element is for promoting crystallization in the amorphous semiconductor film and allows the semiconductor layer to be altered to continuous grain silicon, which leads to higher performance of the TFT. Iron, cobalt, nickel, germanium, ruthenium, rhodium, palladium, osmium, iridium, platinum, copper, gold and the like are used as the catalytic element. The catalytic element preferably contains at least one element selected from the aforementioned group, and Ni is suitably used. A method for adding the catalytic element is not particularly limited. A resistive heating method, a coating method and the like are used as the method for adding the catalytic element.

Thereafter, the amorphous semiconductor layer is crystallized to form a continuous grain silicon layer. A combination of a solid phase crystallization (SPC) method in which crystallization is achieved by annealing treatment and a laser annealing method in which melt recrystallization is achieved by irradiation with excimer laser light and the like is suitable as a method for crystallization.

The continuous grain silicon layer is formed in such a manner, and thereafter, this continuous grain silicon layer is patterned by photolithography and the like to form semiconductor layer 132 and semiconductor layer 180. In this second step, semiconductor layer 123 shown in FIG. 3 is also formed. Although the example in which semiconductor layer 180 and semiconductor layer 123 are formed by the continuous grain silicon layer has been described, a material of semiconductor layer 180 and semiconductor layer 123 is not limited to the continuous grain silicon layer, and other materials may be selected as appropriate.

FIG. 12 is a cross-sectional view showing a third step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 12, the insulating layer made of SiO₂, SiN, SiNO and the like is formed on underlying layer 131 by CVD and the like to cover semiconductor layer 180 and semiconductor layer 132. Gate insulating layer 133 is thus formed.

FIG. 13 is a cross-sectional view showing a fourth step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 13, the stacked metal layers are deposited by sputtering, CVD and the like, and thereafter, the stacked metal layers are patterned by photolithography and the like. As a result, gate electrode 134 and gate electrode 181 are formed.

Gate electrode 134 is formed on a portion of the upper surface of gate insulating layer 133 located above semiconductor layer 132. Gate electrode 181 is formed on a portion of the upper surface of gate insulating layer 133 located above semiconductor layer 180.

In this fourth step, gate line 112, gate line for sensing 113 and gate electrode 122 shown in FIG. 2 are also formed.

FIG. 14 is a cross-sectional view showing a fifth step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 14, interlayer dielectric 135 is formed on the upper surface of gate insulating layer 133 to cover gate electrode 134 and gate electrode 181.

FIG. 15 is a cross-sectional view showing a sixth step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 15, interlayer dielectric 135 and gate insulating layer 133 are patterned by dry etching and the like to form contact holes 162 to 166.

Contact hole 162 and contact hole 163 are formed to reach semiconductor layer 132, and contact hole 164 and contact hole 166 are formed to reach semiconductor layer 180. Contact hole 165 is formed to reach an upper surface of gate electrode 181.

FIG. 16 is a cross-sectional view showing a seventh step of the process of manufacturing TFT array substrate 130. In this FIG. 16, the metal layer is formed by sputtering. At this time, the metal layer also enters contact holes 162 to 166 shown in FIG. 15.

When drain electrodes 137 and 182, source electrodes 138 and 183, lower electrode 172, contact 184, and connection wiring 124 are configured by the stacked metal layers, a plurality of metal layers are stacked sequentially by sputtering.

Then, the formed metal layer or stacked metal layers are patterned to form drain electrodes 137 and 182, source electrodes 138 and 183, lower electrode 172, contact 184, and connection wiring 124.

In this seventh step, source line 111 shown in FIG. 2 as well as source electrode 121 and drain electrode 125 of TFT element for selection 116 are also formed.

Thereafter, upper insulating layer 136 is formed as shown in FIGS. 4 and 5 above. Specifically, the silicon nitride layer (SiN layer) having a thickness of, for example, approximately 200 nm is formed by a plasma enhanced chemical vapor deposition method. Thereafter, upper insulating layer 136 is patterned to form a contact hole for exposing a part of drain electrode 137. Then, an ITO film is formed and this ITO film is patterned to form pixel electrode 114.

When spacer 161 is formed in TFT array substrate 130, a resin layer made of an acrylic resin and the like is formed on the upper surface of upper insulating layer 136 and this resin layer is patterned to form spacer 161. Spacer 161 has a height of approximately 4 μm. TFT array substrate 130 can thus be formed.

As described above, in the method for manufacturing TFT array substrate 130 according to the present embodiment, when the semiconductor layer, the gate electrode, the source electrode, and the drain electrode of TFT element 115 are formed, the semiconductor layers and the like of TFT element for selection 116 and output element 117 can be formed, and the lower electrode of the pressure sensor can also be formed. Therefore, an increase in the number of manufacturing steps is suppressed.

A method for manufacturing common substrate 150 will be described with reference to FIGS. 17 to 21. FIG. 17 is a cross-sectional view showing a first step of a process of manufacturing common substrate 150.

As shown in this FIG. 17, glass substrate 156 having the main surface is prepared. Then, a highly light blocking resin layer having a thickness of approximately 1 to 10 μm is, for example, formed on the main surface of glass substrate 156 by, for example, spin coating and the like. The resin layer preferably has a thickness of approximately 2 to 5 μm. Thereafter, exposure to light, development, cleaning, and post-baking are performed. As a result, black matrix 155 shown in FIG. 2 is formed on the main surface of glass substrate 156. A material of the resin may be a negative type resin or a positive type resin as long as the resin is a photosensitive resin such as an acrylic resin used as a general black photosensitive resin. When the conductivity is provided to black matrix 155, black matrix 155 is made of a conductive resin or a metal such as titanium (Ti).

FIG. 18 is a cross-sectional view showing a second step of the process of manufacturing glass substrate 156. In this FIG. 18, black matrix 155 is a grid-like pattern having an aperture of, for example, approximately 60 μm×100 μm and having a width of approximately 20 μm. Ink of colored layer 153 is applied to the opening of black matrix 155 by an ink-jet method. Color filter substrate 151 is thus formed on the main surface of glass substrate 156. Colored layer 153 has a film thickness of, for example, approximately 1 to 10 μm, and preferably approximately 2 to 5 μm.

FIG. 19 is a cross-sectional view showing a third step of the process of manufacturing common substrate 150. As shown in this FIG. 19, a plastic resin layer 157 made of an acrylic resin and having a film thickness of, for example, approximately 1 to 10 μm is, for example, formed. Plastic resin layer 157 preferably has a film thickness of approximately 1.5 to 5 μm. For example, plastic resin layer 157 has a film thickness of 3.5 μm.

FIG. 20 is a cross-sectional view showing a fourth step of the process of manufacturing common substrate 150. As shown in this FIG. 20, plastic resin layer 157 is patterned by photolithography to form a resin pattern 158. FIG. 21 is a cross-sectional view showing a fifth step of the process of manufacturing common substrate 150. In this FIG. 21, resin pattern 158 is subjected to the annealing treatment (resin annealing) to form projection 170.

Specifically, glass substrate 156 having resin pattern 158 is inserted into an oven and the annealing treatment is performed at a temperature of, for example, 100° C. or higher and 300° C. or lower. The annealing treatment temperature is preferably 100° C. or higher and 200° C. or lower. For example, baking is performed in the oven at 220° C. for approximately 60 minutes.

As a result of the annealing treatment to resin pattern 158, the resin on the surface flows and projection 170 having a smooth surface is formed.

When plastic resin layer 157 has a film thickness of 3.5 μm and patterned resin pattern 158 is subjected to the annealing treatment at 220° C. for 60 minutes, projection 170 has a height of approximately 3.4 μm.

Thereafter, the transparent conductive layer such as the ITO layer is applied to cover projection 170, and thereby common electrode 152 is formed. Common electrode 152 has a film thickness of, for example, approximately 50 nm or more and 400 nm or less. Common electrode 152 preferably has a film thickness of approximately 50 nm or more and 200 nm or less. For example, common electrode 152 has a film thickness of 200 nm.

Common electrode 152 is formed on projection 170 in such a manner, and thereby upper electrode 171 is formed. When spacer 161 is formed on common substrate 150, the resin layer made of an acrylic resin and the like is formed on an upper surface of common electrode 152 and this resin layer is patterned to form spacer 161. Spacer 161 has a height of approximately 4 μm. Common substrate 150 is thus formed.

Then, the liquid crystal layer is applied onto the upper surface of TFT array substrate 130, and further, common substrate 150 is arranged above TFT array substrate 130.

At this time, TFT array substrate 130 and common substrate 150 are stacked such that upper electrode 171 is located above common electrode 152. Thereafter, through various steps, liquid crystal display device 100 shown in FIGS. 4 and 5 can be formed.

When force of approximately 1 N is applied from the TFT array substrate 130 side in liquid crystal display device 100 thus obtained, an electrostatic capacitance that is six times as large as an electrostatic capacitance when the pressing force is not applied can be sensed. Furthermore, the electrostatic capacitance increases in a manner of linear function with respect to the pressing force during a period from the start of pressing to pressing at the force of 1 N.

Second Embodiment

Pressure sensor 118 and liquid crystal display device 100 according to a second embodiment of the present invention will be described with reference to FIGS. 22 to 26. The same reference characters are given to the components shown in FIGS. 22 to 26 that are the same as or corresponding to those shown in FIGS. 1 to 21 above, and description thereof will not be repeated.

FIG. 22 is a cross-sectional view of liquid crystal display device 100 according to the second embodiment and is a cross-sectional view showing TFT element 115. FIG. 23 is a cross-sectional view of liquid crystal display device 100 according to the second embodiment and is a cross-sectional view in output element 117.

As shown in these FIGS. 22 and 23, liquid crystal display device 100 includes TFT element 115 and output element 117, and interlayer dielectric 135 is formed to cover TFT element 115 and output element 117.

Upper ends of drain electrode 137 and source electrode 138 of TFT element 115, upper ends of drain electrode 182 and source electrode 183 of output element 117, an upper end of contact 184, source line 111, and connection wiring 124 are located on the upper surface of interlayer dielectric 135.

A pad unit 185 is formed at the upper end of contact 184, and liquid crystal display device 100 includes an interlayer dielectric 139 formed to cover pad unit 185, the upper ends of drain electrode 137 and source electrode 138 of TFT element 115, the upper ends of drain electrode 182 and source electrode 183 of output element 117, the upper end of contact 184, source line 111, and connection wiring 124.

A reflection electrode 187 and a lower electrode 189 connected to this reflection electrode 187 are formed on the upper surface of this interlayer dielectric 139. Reflection electrode 187 and lower electrode 189 are integrally connected.

Lower electrode 189 and reflection electrode 187 are connected to pad unit 185 by a connection unit 186. Pad unit 185 is connected to gate electrode 181 by contact 184. Lower electrode 189 is connected to gate electrode 181 in such a manner.

Upper insulating layer 136 is formed on lower electrode 189 and reflection electrode 187. Lower electrode 189 is formed into a flat surface. A portion of upper insulating layer 136 located on an upper surface of lower electrode 189 is formed into a flat surface to conform to the upper surface of lower electrode 189.

Pixel electrode 114 shown in FIG. 22 is formed on upper insulating layer 136, passes through upper insulating layer 136 and interlayer dielectric 139, and is connected to drain electrode 137.

Upper electrode 171 is formed on the lower surface of common substrate 150 located above lower electrode 189. In the second embodiment as well, upper electrode 171 includes projection 170 formed on the lower surface of color filter substrate 151, and common electrode 152 formed on the surface of this projection 170.

In liquid crystal display device 100 according to the second embodiment as well, when common substrate 150 is pressed, upper electrode 171 comes into contact with upper insulating layer 136 and projection 170 deforms. Specifically, upper electrode 171 deforms to conform to lower electrode 189. Then, an area of a region where common electrode 152 formed on projection 170 faces lower electrode 189 with upper insulating layer 136 interposed therebetween increases sharply and a potential of lower electrode 189 fluctuates greatly. Therefore, a voltage applied to gate electrode 181 can be fluctuated greatly.

A method for manufacturing liquid crystal display device 100 according to the second embodiment will be described with reference to FIGS. 24 to 26.

A process of manufacturing TFT array substrate 130 of liquid crystal display device 100 according to the second embodiment overlaps partially with the process of manufacturing TFT array substrate 130 of liquid crystal display device 100 according to the first embodiment described above. Specifically, the manufacturing step shown in FIG. 10 to the manufacturing step shown in FIG. 14 are common to manufacturing steps for TFT array substrate 130 in the present embodiment.

FIG. 24 is a cross-sectional view showing a manufacturing step after the manufacturing step shown in FIG. 14, in the process of manufacturing TFT array substrate 130 of liquid crystal display device 100 according to the second embodiment.

As shown in this FIG. 24, interlayer dielectric 135 and gate insulating layer 133 are patterned to form a plurality of contact holes. Thereafter, the metal layer or the stacked metal layers are formed on interlayer dielectric 135.

The metal layer or the stacked metal layers are patterned to form drain electrode 137, source electrode 138, drain electrode 182, contact 184, source electrode 183, pad unit 185, and connection wiring 124. Source line 111 and pad unit 185 are formed on the upper surface of interlayer dielectric 135.

FIG. 25 is a cross-sectional view showing a manufacturing step after the manufacturing step for TFT array substrate 130 shown in FIG. 24. As shown in this FIG. 25, interlayer dielectric 139 is formed to cover source line 111 and pad unit 185.

Then, interlayer dielectric 139 is patterned. At this time, a contact hole is formed at a portion where connection unit 186 will be formed, and projections and recesses are formed at a portion of the upper surface of interlayer dielectric 139 where reflection electrode 187 will be located.

Interlayer dielectric 139 is patterned in such a manner, and thereafter, a metal layer made of aluminum (Al), silver (Ag), molybdenum (Mo) and the like, a metal compound layer containing a metal element such as aluminum (Al), silver (Ag) and molybdenum (Mo), or stacked metal layers formed by stacking an aluminum (Al) layer, a silver (Ag) layer and a molybdenum (Mo) layer is formed on the upper surface of interlayer dielectric 139.

The metal layer or the stacked metal layers are formed on the upper surface of interlayer dielectric 139, and thereby connection unit 186 is formed in the contact hole formed in interlayer dielectric 139.

Then, the metal layer or the stacked metal layers are patterned, and thereby lower electrode 189 and reflection electrode 187 are formed.

Since the projections and recesses are formed in advance at the portion of the upper surface of interlayer dielectric 139 where reflection electrode 187 will be formed, reflection electrode 187 is formed in the shape of projections and recesses to conform to the surface of these projections and recesses.

FIG. 26 is a cross-sectional view showing a manufacturing step for TFT array substrate 130 after the manufacturing step shown in FIG. 25.

As shown in this FIG. 26, upper insulating layer 136 is formed on interlayer dielectric 139 to cover lower electrode 189 and reflection electrode 187.

Thereafter, upper insulating layer 136 and interlayer dielectric 139 are patterned to form a contact hole extending from the upper surface of upper insulating layer 136 to the upper end of drain electrode 137. After the formation of the contact hole, the ITO film is formed on the upper surface of upper insulating layer 136 and this ITO film is patterned to form pixel electrode 114. TFT array substrate 130 shown in FIGS. 22 and 23 is thus formed.

As described above, lower electrode 189 and connection unit 186 connected to this lower electrode 189 can be formed together with reflection electrode 187 in the step of forming reflection electrode 187. Therefore, in the present embodiment as well, the lower electrode of pressure sensor 118 can be formed in TFT array substrate 130 without causing an increase in the number of manufacturing steps.

Third Embodiment

Pressure sensor 118, liquid crystal display device 100 and a method for manufacturing liquid crystal display device 100 according to a third embodiment of the present invention will be described with reference to FIGS. 27 to 37. The same reference characters are given to the components shown in FIGS. 27 to 37 that are the same as or corresponding to those shown in FIGS. 1 to 26 above, and description thereof will not be repeated.

FIG. 27 is a cross-sectional view of liquid crystal display device 100 according to the third embodiment and is a cross-sectional view showing TFT element 115. FIG. 28 is a cross-sectional view of liquid crystal display device 100 according to the third embodiment and is a cross-sectional view showing pressure sensor 118.

As shown in this FIG. 27, liquid crystal display device 100 includes an underlying layer 141 formed on the main surface of glass substrate 140, underlying layer 131 formed on an upper surface of this underlying layer 141, and TFT element 115 formed on underlying layer 131.

Underlying layer 141 is formed of an insulating layer made of SiO₂, SiN, SiNO and the like. Underlying layer 141 has a film thickness of, for example, more than 0 nm and 500 nm or less. Underlying layer 141 preferably has a film thickness of 400 nm or less.

TFT element 115 includes semiconductor layer 132 formed on underlying layer 131, gate electrode 134 formed above semiconductor layer 132 with gate insulating layer 133 interposed therebetween, and drain electrode 137 and source electrode 138 connected to semiconductor layer 132. Gate electrode 134 is covered with interlayer dielectric 135 formed on gate insulating layer 133. Drain electrode 137 and source electrode 138 are formed to reach the upper surface of interlayer dielectric 135. Upper insulating layer 136 is formed on interlayer dielectric 135, and pixel electrode 114 is formed on the upper surface of this upper insulating layer 136. Pixel electrode 114 is connected to the upper end of drain electrode 137.

As shown in FIG. 28, pressure sensor 118 includes lower electrode 172 formed on the upper surface of underlying layer 141, and upper electrode 171 located above lower electrode 172 and arranged to face lower electrode 172. A recess 147 is formed under upper electrode 171 to permit deflection of upper electrode 171. Lower electrode 172 is covered with underlying layer 131. Lower electrode 172 is formed in the shape of a flat plate.

A portion of underlying layer 131 located on lower electrode 172 extends along the upper surface of lower electrode 172 and is formed into a flat surface.

A contact 146 is connected to lower electrode 172, and this contact 146 is formed to reach the upper surface of interlayer dielectric 135. An upper end of contact 146 is connected to source line 111 formed on the upper surface of interlayer dielectric 135.

Upper electrode 171 is formed on the upper surface of gate insulating layer 133, and recess 147 is formed between upper electrode 171 and lower electrode 172 and between gate insulating layer 133 and underlying layer 131.

Upper electrode 171 is formed in the shape of a flat plate. A portion of gate insulating layer 133 located under upper electrode 171 extends along a lower surface of upper electrode 171 and is formed into a flat surface.

Connection wiring 124 is connected to upper electrode 171 and this connection wiring 124 is connected to the drain electrode of TFT element for selection 116 shown in FIG. 1.

Upper insulating layer 136 is formed to cover source line 111 connected to lower electrode 172 and connection wiring 124.

Common substrate 150 of liquid crystal display device 100 according to the third embodiment includes glass substrate 156, color filter substrate 151 formed on a lower surface of this glass substrate 156, common electrode 152 formed on the lower surface of this color filter substrate 151, and a pressing member 145 formed on a lower surface of this common electrode 152. Pressing member 145 is made of a resin such as an acrylic resin.

Control unit 105 senses source line 111 connected to contact 146 and an output of source line 111 connected to TFT element for selection 116.

As a result, control unit 105 can sense the capacitance between upper electrode 171 and lower electrode 172. Control unit 105 calculates the pressing force applied to common substrate 150, based on fluctuations in the capacitance between upper electrode 171 and lower electrode 172.

When a user presses common substrate 150 using a pen or his/her finger, a pressed portion of common substrate 150 deflects slightly.

FIG. 29 is a cross-sectional view schematically showing a state of liquid crystal display device 100 when common substrate 150 is pressed.

As shown in this FIG. 29, when pressing member 145 presses the upper surface of TFT array substrate 130, upper electrode 171 and gate insulating layer 133 located under this upper electrode 171 deflect.

Then, gate insulating layer 133 located under upper electrode 171 abuts underlying layer 131 located on lower electrode 172, and upper electrode 171 deforms.

FIG. 30 is a cross-sectional view showing upper electrode 171 and gate insulating layer 133 before upper electrode 171 and gate insulating layer 133 are deformed by the pressing force from pressing member 145.

As shown in this FIG. 30, a plurality of holes 173 and 174 are formed in upper electrode 171 and gate insulating layer 133. Holes 173 and holes 174 are formed to communicate with one another.

FIG. 31 is a plan view of upper electrode 171. As shown in this FIG. 31, upper electrode 171 is formed to have a substantially square shape, and hole 173 formed in upper electrode 171 is also formed to have a square shape. Holes 173 are formed in upper electrode 171 to be evenly distributed. One side of upper electrode 171 has a length of, for example, approximately 30 μm and one side of hole 173 has a length of, for example, approximately 2 μm. Upper electrode 171 is formed to have a width larger than a width of gate electrode 134. Therefore, upper electrode 171 is easily deformed by the external pressing force.

Upper electrode 171 is formed to have a film thickness of, for example, 50 nm or more and 600 nm or less, and preferably 100 nm or more and 500 nm or less.

As described above, upper electrode 171 is formed to have a length of a side that is much larger than a thickness of upper electrode 171. Therefore, upper electrode 171 can deform to easily deflect when a central portion of an upper surface of upper electrode 171 is pressed.

Upper electrode 171 is made of a metal that is the same as that of the gate electrode. Upper electrode 171 is formed of, for example, a metal layer made of tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or an alloy containing an element such as tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo), or a compound containing tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo).

Preferably, upper electrode 171 and the gate electrode are formed of a tungsten (W) layer having a thickness of approximately 370 nm and a TaN (tantalum nitride) layer having a thickness of approximately 50 nm and formed on this tungsten (W) layer.

The shape of upper electrode 171 is not limited to the square shape and may be a rectangular shape. Various types of shapes such as a shape of a polygon more than a pentagon, a circular shape, and an oval shape can be used.

FIG. 32 is a cross-sectional view showing a state where upper electrode 171 and gate insulating layer 133 have been deformed by the pressing force from pressing member 145.

As shown in this FIG. 32, gate insulating layer 133 and upper electrode 171 deflect to go into recess 147.

An opening edge of recess 147 is slightly smaller than an outer edge of upper electrode 171 and most of upper electrode 171 deflects to enter recess 147.

Recess 147 is formed by a hole formed in semiconductor layer 180 and the upper surface of underlying layer 131. Therefore, a height of recess 147 is the same as a thickness of semiconductor layer 180. Semiconductor layer 180 is formed to have a thickness of, for example, 20 nm or more and 200 nm or less, and preferably 30 nm or more and 70 nm or less. The length of one side of upper electrode 171 is much larger than the height of recess 147.

Therefore, when upper electrode 171 and gate insulating layer 133 slightly deform, gate insulating layer 133 abuts the upper surface of underlying layer 131.

Furthermore, when upper electrode 171 and gate insulating layer 133 are pressed by pressing member 145, most of a portion of gate insulating layer 133 located in recess 147 abuts underlying layer 131 as shown in FIG. 32.

At this time, gate insulating layer 133 deforms to conform to the upper surface of underlying layer 131, and upper electrode 171 located on gate insulating layer 133 also deforms to conform to underlying layer 131.

Since underlying layer 131 is formed into a flat surface along the upper surface of lower electrode 172, upper electrode 171 deforms into a flat surface to conform to the shape of lower electrode 172.

Therefore, gate insulating layer 133 and underlying layer 131 are sandwiched between most of upper electrode 171 and lower electrode 172, and most of upper electrode 171 faces lower electrode 172 with gate insulating layer 133 and underlying layer 131 interposed therebetween.

FIG. 33 is a plan view of upper electrode 171 when upper electrode 171 has been deformed as shown in FIG. 32. In this FIG. 33, a region enclosed by a broken line represents a region where upper electrode 171 has deformed to conform to the upper surface of lower electrode 172, and this region enclosed by the broken line is a region facing underlying layer 131 and underlying layer 141 with underlying layer 131 interposed therebetween.

As shown in this FIG. 33, as a result of slight deformation of upper electrode 171, most of upper electrode 171 deforms to conform to lower electrode 172.

When pressing member 145 is slightly displaced downward, an area of this region enclosed by the broken line increases sharply. Therefore, the capacitance between upper electrode 171 and lower electrode 172 also increases sharply.

As described above, in pressure sensor 118 according to the third embodiment as well, the upper electrode deforms to conform to the shape of the lower electrode, and the characteristic of pressure sensor 118 exhibits the characteristic shown by the solid line in FIG. 8.

Therefore, liquid crystal display device 100 according to the third embodiment can accurately calculate the pressure applied to common substrate 150.

A method for manufacturing liquid crystal display device 100 according to the third embodiment will be described with reference to FIGS. 34 to 36. In liquid crystal display device 100 according to the third embodiment as well, TFT array substrate 130 and common substrate 150 are independently formed. Thereafter, TFT array substrate 130 and common substrate 150 are arranged to face each other.

FIG. 34 is a cross-sectional view showing a first step of a process of manufacturing TFT array substrate 130. As shown in this FIG. 34, glass substrate 140 having the main surface is prepared. Underlying layer 141 is formed on the main surface of this glass substrate 140. Underlying layer 141 is formed of, for example, an insulating layer made of SiO₂, SiN, SiNO and the like, and is formed of, for example, a silicon oxynitride layer (SiNO layer) having a thickness of approximately 50 nm and a silicon oxide layer (SiO₂ layer) having a thickness of approximately 110 nm and formed on this silicon oxynitride layer (SiNO layer).

Underlying layer 141 is formed to have a film thickness of, for example, more than 0 nm and 500 nm or less. Underlying layer 141 is preferably formed to have a film thickness of 400 nm or less.

Thereafter, a metal layer made of molybdenum (Mo), tungsten (W) and the like is formed on the upper surface of underlying layer 141 by sputtering and the like. Then, this metal layer is patterned to form lower electrode 172. Lower electrode 172 is formed to have a film thickness of, for example, 50 nm or more and 600 nm or less. Lower electrode 172 is formed to have a film thickness of 50 nm or more and 300 nm or less.

The insulating layer made of SiO₂, SiN, SiNO and the like is formed to cover lower electrode 172, and underlying layer 131 is formed. Underlying layer 131 has a film thickness of approximately 50 nm or more and 400 nm or less, and preferably 50 nm or more and 200 nm or less.

The amorphous semiconductor layer is deposited on underlying layer 141. The amorphous semiconductor layer has a film thickness of, for example, 20 nm or more and 200 nm or less. The amorphous semiconductor layer preferably has a film thickness of approximately 30 nm or more and 70 nm. Thereafter, this amorphous semiconductor layer is crystallized to form the continuous grain silicon layer. The continuous grain silicon layer is patterned to form semiconductor layer 132 and semiconductor layer 180. Semiconductor layer 180 is formed on a portion of the upper surface of underlying layer 131 located above lower electrode 172.

FIG. 35 is a cross-sectional view showing a second step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 35, the insulating layer made of SiO₂, SiN, SiNO and the like is formed, and gate insulating layer 133 is formed. Gate insulating layer 133 has a film thickness of, for example, 20 nm or more and 200 nm or less, and preferably 50 nm or more and 120 nm or less. Specifically, gate insulating layer 133 is formed of a SiO2 layer having a thickness of approximately 80 nm.

After the formation of gate insulating layer 133, P+ is doped into semiconductor layer 132 and semiconductor layer 180 under the conditions of 45 KV and 5E15 cm⁻².

Then, the metal layer is formed on the upper surface of gate insulating layer 133. This metal layer is formed of, for example, a metal film made of tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or an alloy film containing tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or a compound containing an element such as tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo).

This metal layer has a film thickness of, for example, 50 nm or more and 600 nm or less, and preferably 100 nm or more and 500 nm or less.

Thereafter, this metal layer is patterned to form gate electrode 134 and upper electrode 171. At this time, hole 173 is simultaneously formed in upper electrode 171.

In other words, in the method for manufacturing liquid crystal display device 100 according to the third embodiment, gate electrode 134 and upper electrode 171 can be simultaneously formed and an increase in the number of manufacturing steps is suppressed.

After the formation of upper electrode 171 and gate electrode 134, a resist mask covering a portion other than upper electrode 171 is formed, and gate insulating layer 133 is etched using upper electrode 171 and this mask. Gate insulating layer 133 is etched using an acid-based solution such as an HF (hydrogen fluoride) aqueous solution. As a result, hole 174 is formed in gate insulating layer 133.

FIG. 36 is a cross-sectional view showing a third step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 36, a resist is first formed on the upper surface of gate insulating layer 133 to cover upper electrode 171 and gate electrode 134, and this resist is patterned. A resist pattern 223 is thus formed. This resist pattern 223 has a hole to expose hole 173 and hole 174 to the outside. Then, the substrate is immersed in an alkaline solution containing potassium hydroxide (KOH) and the like. The solution flows in through hole 173 and hole 174, and semiconductor layer 180 is etched. As a result, recess 147 is formed in semiconductor layer 180.

Thereafter, as shown in FIG. 28, resist pattern 223 is first removed and interlayer dielectric 135 is formed to cover gate electrode 134 and upper electrode 171. Interlayer dielectric 135 is patterned to form a plurality of contact holes, and thereafter, the metal layer is formed on the upper surface of interlayer dielectric 135 by sputtering. This metal layer is patterned to form drain electrode 137, source electrode 138, source line 111, contact 146, and connection wiring 124.

Then, upper insulating layer 136 is deposited and this upper insulating layer 136 is patterned to form a contact hole. Thereafter, the ITO film is deposited and this ITO film is patterned to form pixel electrode 114. TFT array substrate 130 of liquid crystal display device 100 according to the third embodiment is thus formed.

On the other hand, in order to form common substrate 150, glass substrate 156 is first prepared. Color filter substrate 151 is formed on the main surface of this glass substrate 156, and thereafter, common electrode 152 is formed. Then, a resin such as an acrylic resin is deposited on this common electrode 152. This acrylic resin is patterned to form pressing member 145. Common substrate 150 of liquid crystal display device 100 according to the third embodiment is thus formed. Thereafter, liquid crystal layer 160 is applied onto the upper surface of formed TFT array substrate 130, and common substrate 150 is arranged on the upper surface side of TFT array substrate 130. Liquid crystal display device 100 according to the present embodiment is thus formed.

FIG. 37 is a cross-sectional view showing a modification of TFT array substrate 130 shown in FIG. 28. In the example shown in this FIG. 37, a light blocking layer 148 is formed on a portion of the upper surface of underlying layer 141 located below semiconductor layer 132. This light blocking layer 148 is made of a material that is the same as (a material of the same kind as) that of lower electrode 172, and a film thickness of light blocking layer 148 is substantially identical to a film thickness of lower electrode 172. Specifically, light blocking layer 148 is formed of, for example, a metal film made of tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or an alloy film containing tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or a compound containing an element such as tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo). Light blocking layer 148 has a film thickness of, for example, 50 nm or more and 600 nm or less, and preferably 100 nm or more and 500 nm or less.

Light blocking layer 148 suppresses irradiation of semiconductor layer 132 with light and suppresses fluctuations in characteristic of TFT element 115 caused by a photoelectric effect.

In the process of manufacturing TFT array substrate 130, light blocking layer 148 and lower electrode 172 are formed by patterning the metal layer deposited on underlying layer 141. Since lower electrode 172 and light blocking layer 148 can be formed in the same step as described above, an increase in the number of steps of manufacturing liquid crystal display device 100 is suppressed and lower electrode 172 and light blocking layer 148 can be formed.

Fourth Embodiment

Pressure sensor 118, liquid crystal display device 100 and a method for manufacturing liquid crystal display device 100 according to a fourth embodiment of the present invention will be described with reference to FIGS. 38 to 49. The same reference characters are given to the components shown in FIGS. 38 to 49 that are the same as or corresponding to those shown in FIGS. 1 to 37 above, and description thereof will not be repeated.

FIG. 38 is a circuit diagram schematically showing a circuit diagram of liquid crystal display device 100 according to the fourth embodiment.

As shown in this FIG. 38, one electrode (lower electrode) of a pressure sensor 190 according to the fourth embodiment is connected to the drain electrode of TFT element for selection 116, and the other electrode (upper electrode) of pressure sensor 190 is connected to common electrode 152.

By switching ON/OFF of TFT element for selection 116, control unit 105 selects pressure sensor 190 for sensing.

In order to turn on selected TFT element for selection 116, a predetermined voltage is applied to gate line for sensing 113 to which selected TFT element for selection 116 is connected. A predetermined voltage is applied to source line 111 to which the source electrode of this selected TFT element for selection 116 is connected.

Pressure sensor 190 is formed to change an amount of current in accordance with the externally applied pressure.

Therefore, by sensing an amount of current flowing between source line 111 to which TFT element for selection 116 is connected and common electrode 152, control unit 105 can calculate the pressure applied to selected pressure sensor 190.

FIG. 39 is a cross-sectional view of liquid crystal display device 100 according to the fourth embodiment and is a cross-sectional view showing TFT element 115.

As shown in this FIG. 39, liquid crystal display device 100 includes TFT array substrate 130, common substrate 150 arranged above TFT array substrate 130, and liquid crystal layer 160 filled between TFT array substrate 130 and common substrate 150.

TFT array substrate 130 includes glass substrate 140, underlying layer 131 formed on the main surface of glass substrate 140, and TFT element 115 formed on this underlying layer 131.

TFT element 115 includes semiconductor layer 132 formed on underlying layer 131, gate insulating layer 133 formed to cover semiconductor layer 132, gate electrode 134 formed on this gate insulating layer 133, and drain electrode 137 and source electrode 138 connected to semiconductor layer 132.

Interlayer dielectric 135 is formed on gate insulating layer 133 to cover gate electrode 134, and drain electrode 137 and source electrode 138 are formed to reach the upper surface of this interlayer dielectric 135. A drain pad 210 is formed at the upper end of drain electrode 137, and pixel electrode 114 is connected to drain pad 210.

A wiring 211 is formed at the upper end of source electrode 138, and a transparent conductive layer 212 is formed on an upper surface of this wiring 211. Wiring 211 and transparent conductive layer 212 constitute source line 111 to which TFT element 115 is connected.

Spacer 161 is arranged between common substrate 150 and TFT array substrate 130.

FIG. 40 is a cross-sectional view of liquid crystal display device 100 according to the fourth embodiment and is a cross-sectional view showing TFT element for selection 116 and pressure sensor 190.

As shown in this FIG. 40, TFT element for selection 116 is formed in TFT array substrate 130, and pressure sensor 190 is formed between common substrate 150 and TFT array substrate 130.

TFT element for selection 116 includes a semiconductor layer 200 formed on underlying layer 131, gate insulating layer 133 formed to cover this semiconductor layer 200, a gate electrode 201 formed on the upper surface of gate insulating layer 133, and a drain electrode 202 and a source electrode 203 connected to semiconductor layer 200.

Interlayer dielectric 135 is formed on gate insulating layer 133 to cover gate electrode 201. An upper end of drain electrode 202 is formed to reach the upper surface of interlayer dielectric 135, and an electrode unit 213 is connected to the upper end of drain electrode 202. Electrode unit 213 is located on the upper surface of interlayer dielectric 135 and is formed into a flat surface.

An upper end of source electrode 203 is formed to reach the upper surface of interlayer dielectric 135, and a wiring 214 is connected to this upper end of source electrode 203. Wiring 214 is located on the upper surface of interlayer dielectric 135 and is formed into a flat surface. A transparent conductive layer 215 is formed on an upper surface of wiring 214, and transparent conductive layer 215 is formed of an ITO layer and the like. Wiring 214 and transparent conductive layer 215 constitute source line 111 to which TFT element for selection 116 is connected.

Pressure sensor 190 includes upper electrode 171 formed in common substrate 150, and a lower electrode 191 formed in TFT array substrate 130.

Upper electrode 171 is formed by projection 170 formed on the lower surface of color filter substrate 151, and common electrode 152 located on this projection 170. Projection 170 is made of a plastic resin such as an acrylic resin and is elastically deformable.

Lower electrode 191 is formed on an upper surface of electrode unit 213. Lower electrode 191 is formed of, for example, a transparent conductive layer such as an ITO film, and a resistance layer made of Si and the like. Lower electrode 191 has a film thickness of, for example, 50 nm or more and 400 nm or less, and preferably 50 nm or more and 200 nm or less.

In the example shown in this FIG. 40, in a state where the external force is not applied to common substrate 150, a small gap is formed between upper electrode 171 and lower electrode 191.

In the state where the external force is not applied to common substrate 150, upper electrode 171 is not in contact with lower electrode 191 and a current does not flow between upper electrode 171 and lower electrode 191. Therefore, electric power consumption is reduced.

FIG. 41 is a cross-sectional view schematically showing a state where common substrate 150 is pressed. As shown in this FIG. 41, when common substrate 150 is pressed, common substrate 150 deforms and upper electrode 171 comes into contact with lower electrode 191.

As a result of contact between upper electrode 171 and lower electrode 191, a current flows between upper electrode 171 and lower electrode 191. By sensing source line 111 to which TFT element for selection 116 is connected and common electrode 152, control unit 105 can sense an amount of current flowing between lower electrode 191 and upper electrode 171.

When the pressure at which common substrate 150 is pressed increases, projection 170 deforms. As a result of deformation of projection 170, a portion of common electrode 152 located on projection 170 also deforms to conform to the shape of lower electrode 191.

As a result, a contact area between lower electrode 191 and common electrode 152 increases sharply, and the amount of current flowing between lower electrode 191 and upper electrode 171 also increases. Therefore, control unit 105 can easily sense changes in the amount of current and easily calculate the pressing force applied to common substrate 150.

Therefore, in pressure sensor 190 and liquid crystal display device 100 according to the fourth embodiment as well, the pressing force applied to common substrate 150 can be accurately sensed. Upper electrode 171 may be in slight contact with lower electrode 191 in the initial state. In this case, by only applying small pressing force to common substrate 150, the amount of current flowing between upper electrode 171 and lower electrode 191 can be changed.

A method for manufacturing liquid crystal display device 100 according to the fourth embodiment will be described with reference to FIGS. 42 to 49.

In liquid crystal display device 100 according to the fourth embodiment as well, liquid crystal display device 100 is formed by separately forming common substrate 150 and TFT array substrate 130, and thereafter, assembling common substrate 150 and TFT array substrate 130 together so as to sandwich the liquid crystal layer.

FIG. 42 is a cross-sectional view showing a first step of a process of manufacturing TFT array substrate 130. As shown in this FIG. 42, glass substrate 140 having the main surface is prepared. Underlying layer 131 is formed on the main surface of glass substrate 140. Underlying layer 131 is formed of an insulating layer made of SiO₂, SiN, SiNO and the like. Underlying layer 131 is formed to have a film thickness of, for example, 500 nm or less, and preferably 400 nm or less.

Thereafter, the amorphous semiconductor layer is deposited on the upper surface of underlying layer 131. The amorphous semiconductor layer has a film thickness of, for example, 20 nm or more and 200 nm or less. The amorphous semiconductor layer preferably has a film thickness of approximately 30 nm or more and 70 nm. Thereafter, this amorphous semiconductor layer is crystallized to form the continuous grain silicon layer. The continuous grain silicon layer is patterned to form semiconductor layer 132 and semiconductor layer 200.

As described above, semiconductor layer 132 of TFT element 115 and semiconductor layer 200 of TFT element for selection 116 can be formed in the same patterning step.

FIG. 43 is a cross-sectional view showing a second step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 43, gate insulating layer 133 is formed on underlying layer 131 to cover semiconductor layer 132 and semiconductor layer 200. Gate insulating layer 133 is formed of an insulating layer made of SiO₂, SiN, SiNO and the like. Gate insulating layer 133 has a film thickness of, for example, 20 nm or more and 200 nm or less, and preferably 50 nm or more and 120 nm or less.

The metal layer is formed on the upper surface of gate insulating layer 133 by sputtering and the like. This metal layer is formed of, for example, a metal film made of tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or an alloy film containing tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or a compound containing an element such as tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo). This metal layer has a film thickness of, for example, 50 nm or more and 600 nm or less, and preferably 100 nm or more and 500 nm or less.

Then, this metal layer is patterned to form gate electrode 134 and gate electrode 201. As described above, gate electrode 134 of TFT element 115 and gate electrode 201 of TFT element for selection 116 can be formed in the same patterning step.

FIG. 44 is a cross-sectional view showing a third step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 44, interlayer dielectric 135 is formed to cover gate electrode 201 and gate electrode 134. Interlayer dielectric 135 is formed of, for example, an insulating layer made of SiO₂, SiN, SiNO and the like. Interlayer dielectric 135 is formed to have a film thickness of, for example, 100 nm or more and 1000 nm or less. Interlayer dielectric 135 preferably has a film thickness of 100 nm or more and 700 nm or less.

Interlayer dielectric 135 is patterned to form a plurality of contact holes. After the formation of the contact holes, a conductive layer is formed on interlayer dielectric 135 by sputtering. This metal layer is formed of a metal layer made of tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or an alloy containing an element such as tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo), or a compound containing tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo).

This metal layer is patterned to form drain electrode 137, drain pad 210, source electrode 138, wiring 211, drain electrode 202, electrode unit 213, source electrode 203, and wiring 214.

Thereafter, the transparent conductive layer made of ITO and the like is formed to cover drain pad 210, wiring 211, electrode unit 213, and wiring 214. This transparent conductive layer is patterned to form pixel electrode 114, transparent conductive layer 212, lower electrode 191, and transparent conductive layer 215 shown in FIGS. 39 and 40.

As a result, TFT array substrate 130 shown in FIGS. 39 and 40 can be formed. As described above, in the method for manufacturing liquid crystal display device 100 according to the fourth embodiment, TFT element for selection 116 and lower electrode 191 of pressure sensor 190 can be formed in the process of forming TFT element 115, and thus, an increase in the number of manufacturing steps is suppressed.

FIG. 45 is a cross-sectional view showing a first step of a process of manufacturing common substrate 150. As shown in this FIG. 45, glass substrate 156 having the main surface is prepared. Then, color filter substrate 151 is formed on the main surface of this glass substrate 156.

FIG. 46 is a cross-sectional view showing a second step of the process of manufacturing common substrate 150. As shown in this FIG. 46, plastic resin layer 157 is formed on the main surface of color filter substrate 151.

Plastic resin layer 157 has a film thickness of, for example, approximately 1 to 10 μm, and preferably approximately 2 to 5 μm.

FIG. 47 is a cross-sectional view showing a third step of the process of manufacturing common substrate 150. As shown in this FIG. 47, plastic resin layer 157 is patterned to form resin pattern 158. FIG. 48 is a cross-sectional view showing a fourth step of the process of manufacturing common substrate 150. In this FIG. 48, resin pattern 158 is subjected to the annealing treatment to form projection 170 having a smooth surface.

FIG. 49 is a cross-sectional view showing a fifth step of the process of manufacturing common substrate 150. As shown in this FIG. 49, common electrode 152 is formed on the surface of color filter substrate 151 to cover projection 170. The upper electrode is thus formed.

After the formation of common electrode 152, the resin layer made of an acrylic resin and the like is formed. This resin layer is patterned to form a plurality of spacers 161. Common electrode 152 and TFT array substrate 130 thus formed are assembled together. Liquid crystal display device 100 is thus formed.

Fifth Embodiment

Pressure sensor 118, liquid crystal display device 100 and a method for manufacturing liquid crystal display device 100 according to a fifth embodiment of the present invention will be described with reference to FIGS. 50 to 57 and FIG. 38. The same reference characters are given to the components shown in FIGS. 50 to 57 that are the same as or corresponding to those shown in FIGS. 1 to 49 above, and description thereof will not be repeated. In addition, an electrical circuit of liquid crystal display device 100 according to the fifth embodiment corresponds to the electrical circuit shown in FIG. 38 above.

FIG. 50 is a cross-sectional view of liquid crystal display device 100 according to the fifth embodiment and is a cross-sectional view showing TFT element 115.

As shown in this FIG. 50, liquid crystal display device 100 includes glass substrate 140, underlying layer 131 formed on the main surface of this glass substrate 140, and TFT element 115 formed on the upper surface of underlying layer 131.

TFT element 115 includes semiconductor layer 132 formed on underlying layer 131, gate insulating layer 133 formed on underlying layer 131 to cover semiconductor layer 132, gate electrode 134 formed on this gate insulating layer 133, and drain electrode 137 and source electrode 138 connected to semiconductor layer 132.

Interlayer dielectric 135 is formed on gate insulating layer 133 to cover gate electrode 134. Drain pad 210 and source line 111 are formed on the upper surface of this interlayer dielectric 135. Drain electrode 137 is connected to drain pad 210, and source electrode 138 is connected to source line 111.

Furthermore, a resin layer 149 is formed on the upper surface of interlayer dielectric 135. Resin layer 149 is made of a plastic resin such as an acrylic resin. Resin layer 149 has a film thickness of, for example, 1 μm or more and 10 μm or less. Resin layer 149 preferably has a film thickness of 1.5 μm or more and 5 μm or less. Pixel electrode 114 is formed on an upper surface of resin layer 149 and pixel electrode 114 is connected to drain pad 210.

FIG. 51 is a cross-sectional view of liquid crystal display device 100 and is a cross-sectional view showing TFT element for selection 116.

As shown in this FIG. 51, liquid crystal display device 100 includes TFT element for selection 116 formed on underlying layer 131.

TFT element for selection 116 includes semiconductor layer 180 formed on underlying layer 131, gate insulating layer 133 formed on underlying layer 131 to cover semiconductor layer 180, gate electrode 181 formed on this gate insulating layer 133, and drain electrode 182 and source electrode 183 connected to semiconductor layer 180.

A pad unit 219, source line 111 and a lower electrode 218 are formed on the upper surface of interlayer dielectric 135. The upper end of drain electrode 182 is connected to pad unit 219, and the upper end of source electrode 183 is connected to source line 111.

Therefore, by controlling a voltage applied to gate electrode 181, ON/OFF of TFT element for selection 116 can be switched.

Lower electrode 218 is connected to pad unit 219. Lower electrode 218 includes a projection 216 formed to protrude upward from the upper surface of interlayer dielectric 135 and a conductive layer 217 formed on a surface of this projection 216. Projection 216 is made of a material that is the same as that of resin layer 149 and projection 216 is made of, for example, an elastically deformable resin such as an acrylic resin. Projection 216 has a curved outer surface. Conductive layer 217 is connected to pad unit 219.

Upper electrode 171 is formed on a portion of the lower surface of common substrate 150 located above lower electrode 218.

Upper electrode 171 is formed by spacer 161 formed on the lower surface of color filter substrate 151, and common electrode 152 foamed on the lower surface of color filter substrate 151 to cover this spacer 161. Spacer 161 is made of for example, an acrylic resin and is formed to protrude from the lower surface of color filter substrate 151 toward lower electrode 218.

When control unit 105 performs sensing, a predetermined voltage is applied to gate electrode 181 and TFT element for selection 116 is turned on.

When common substrate 150 is pressed, upper electrode 171 is displaced toward lower electrode 218 and upper electrode 171 presses lower electrode 218. Conductive layer 217 is pressed, and thereby conductive layer 217 deforms and lower electrode 218 deforms to conform to the surface shape of upper electrode 171. As a result, a contact area between common electrode 152 of upper electrode 171 and conductive layer 217 of lower electrode 218 increases sharply. Consequently, an amount of current flowing between common electrode 152 and conductive layer 217 increases.

By sensing the amount of current between common electrode 152 and source line 111 to which TFT element for selection 116 is connected, control unit 105 shown in FIG. 38 calculates the pressure applied to common substrate 150.

As described above, in liquid crystal display device 100 according to the fifth embodiment as well, the pressure applied to common substrate 150 can be accurately calculated because the amount of current flowing between upper electrode 171 and lower electrode 218 changes greatly when common substrate 150 is pressed.

A method for manufacturing liquid crystal display device 100 according to the fifth embodiment will be described with reference to FIGS. 52 to 57. In liquid crystal display device 100 according to the fifth embodiment as well, liquid crystal display device 100 is formed by independently forming TFT array substrate 130 and common substrate 150, and thereafter, assembling TFT array substrate 130 and common substrate 150 together.

FIG. 52 is a cross-sectional view showing a step when TFT element 115 and TFT element for selection 116 are formed, in a process of manufacturing TFT array substrate 130.

In this FIG. 52, the continuous grain silicon layer is formed from the amorphous semiconductor layer, and thereafter, this continuous grain silicon layer is patterned by photolithography and the like to form semiconductor layer 132 and semiconductor layer 180.

After the formation of semiconductor layer 132 and semiconductor layer 180, gate insulating layer 133 is formed on underlying layer 131. Gate electrode 134 and gate electrode 181 are formed by patterning the same metal layer formed on gate insulating layer 133.

After the formation of gate electrode 134 and gate electrode 181, interlayer dielectric 135 is formed. Drain pad 210, drain electrode 137, source electrode 138, pad unit 219, drain electrode 182, source electrode 183, and source line 111 are formed by patterning the same metal layer formed on interlayer dielectric 135.

FIG. 53 is a cross-sectional view showing a manufacturing step for TFT array substrate 130 after the manufacturing step shown in FIG. 52. As shown in this FIG. 53, an acrylic resin is formed on interlayer dielectric 135. Thereafter, this acrylic resin is patterned to form a projection 221 and resin layer 149. Projection 221 is located on interlayer dielectric 135 and projection 221 is located in a recess 220 formed in resin layer 149.

FIG. 54 is a cross-sectional view showing a manufacturing step after the manufacturing step shown in FIG. 53. As shown in this FIG. 54, glass substrate 140 having projection 221 is subjected to the annealing treatment in the oven. The annealing temperature is set to be, for example, 100° C. or higher and 300° C. or lower, and preferably 100° C. or higher and 200° C. or lower.

As a result, the resin on a surface of projection 221 flows and projection 216 having a curved surface is formed.

After the formation of projection 216 in such a manner, the transparent conductive layer made of ITO and the like is formed to cover resin layer 149 and projection 216. This transparent conductive layer is patterned to form pixel electrode 114 and conductive layer 217 shown in FIGS. 50 and 51. As a result, lower electrode 218 can be formed and TFT array substrate 130 can be formed.

FIG. 55 is a cross-sectional view showing formation of color filter substrate 151 in a process of manufacturing common substrate 150. As shown in this FIG. 55, color filter substrate 151 is formed on glass substrate 156.

FIG. 56 is a cross-sectional view showing a step after the manufacturing step shown in FIG. 55 above. As shown in this FIG. 56, the resin layer made of an acrylic resin and the like is formed on an upper surface of color filter substrate 151. Then, this resin layer is patterned to form a plurality of spacers 161.

FIG. 57 is a cross-sectional view showing a step after the manufacturing step shown in FIG. 56 above. As shown in this FIG. 57, the transparent conductive layer made of ITO and the like is formed. Common substrate 150 including upper electrode 171 and common electrode 152 is thus formed.

Then, common substrate 150 and TFT array substrate 130 are assembled together and liquid crystal display device 100 is thus formed.

Sixth Embodiment

A sixth embodiment of the present invention will be described with reference to FIGS. 58 to 74. The same reference characters are given to the components shown in FIGS. 58 to 74 that are the same as or corresponding to those shown in FIGS. 1 to 57 above, and description thereof will not be repeated.

FIG. 58 is a circuit diagram showing an electrical circuit of liquid crystal display device 100 according to the sixth embodiment. As shown in this FIG. 58, pressure sensor 190 is connected to the drain electrode of TFT element for selection 116 and source line 111.

FIG. 59 is a cross-sectional view of liquid crystal display device 100 according to the sixth embodiment and is a cross-sectional view showing TFT element 115.

FIG. 60 is a cross-sectional view of liquid crystal display device 100 according to the sixth embodiment and is a cross-sectional view showing pressure sensor 190.

In these FIGS. 59 and 60, pressure sensing element 120 includes underlying layer 131 formed on the main surface of glass substrate 140, and TFT element 115 and pressure sensor 190 formed on underlying layer 131.

TFT element 115 includes semiconductor layer 132, gate electrode 134, drain electrode 137, and source electrode 138.

Pressure sensor 190 includes semiconductor layer 180 formed on underlying layer 131, and upper electrode 171 spaced apart from this semiconductor layer 180 and formed to face semiconductor layer 180. Semiconductor layer 180 functions as the lower electrode of pressure sensor 190.

Semiconductor layer 132 and semiconductor layer 180 are formed on the upper surface of underlying layer 131.

Gate insulating layer 133 is formed on underlying layer 131 to cover semiconductor layer 132 and semiconductor layer 180.

Gate electrode 134 is formed on a portion of the upper surface of gate insulating layer 133 located above semiconductor layer 132, and upper electrode 171 is formed on a portion of the upper surface of gate insulating layer 133 located above semiconductor layer 180.

Interlayer dielectric 135 is formed on the upper surface of gate insulating layer 133 to cover gate electrode 134 and upper electrode 171.

Drain electrode 137, source electrode 138, contact 146, and connection wiring 124 are formed to reach the upper surface of interlayer dielectric 135. Connection wiring 124 is connected to TFT element for selection 116 shown in FIG. 58 and the other end thereof is connected to upper electrode 171. The upper end of contact 146 is connected to source line 111 and a lower end of contact 146 is connected to semiconductor layer 180.

Drain electrode 137 and source electrode 138 are connected to semiconductor layer 132, and drain pad 210 is connected to the upper end of drain electrode 137. Source line 111 is connected to the upper end of source electrode 138. Drain pad 210 and source line 111 are formed on interlayer dielectric 135.

Upper insulating layer 136 is formed to cover drain pad 210, source line 111 and connection wiring 124.

Pixel electrode 114 is formed on upper insulating layer 136 and is connected to drain pad 210.

Pressing member 145 is formed on a portion of the lower surface of common substrate 150 located above upper electrode 171. Pressing member 145 is formed to protrude from the lower surface of common substrate 150 toward TFT array substrate 130.

Recess 147 is formed directly under upper electrode 171. This recess 147 is formed by a hole formed in gate insulating layer 133 and an upper surface of semiconductor layer 180.

In the example shown in this FIG. 60, in the state where common substrate 150 is not pressed, a lower end of pressing member 145 abuts the upper surface of upper insulating layer 136.

FIG. 61 is a cross-sectional view showing upper electrode 171 and semiconductor layer 180 in the state (initial state) where common substrate 150 is not pressed.

As shown in this FIG. 61, in the initial state, upper electrode 171 is spaced apart from semiconductor layer 180 and upper electrode 171 is not in contact with semiconductor layer 180. FIG. 62 is a plan view of upper electrode 171. A plurality of holes 173 are formed in upper electrode 171.

FIG. 63 is a cross-sectional view showing upper electrode 171 and semiconductor layer 180 in the state where common substrate 150 has been pressed. As shown in this FIG. 63, when common substrate 150 is pressed, upper electrode 171 comes into contact with semiconductor layer 180. When the pressing force by which common substrate 150 is pressed is small, a contact area between upper electrode 171 and semiconductor layer 180 is small and an amount of current flowing between semiconductor layer 180 and upper electrode 171 is small.

Then, the pressing force by which common substrate 150 is pressed increases, upper electrode 171 deflects greatly, upper electrode 171 deforms to conform to semiconductor layer 180, and the contact area between upper electrode 171 and semiconductor layer 180 increases.

A region enclosed by a broken line in FIG. 62 represents an area of contact between upper electrode 171 and semiconductor layer 180.

As shown in these FIGS. 62 and 63, when the contact area between upper electrode 171 and semiconductor layer 180 increases, the amount of current flowing between upper electrode 171 and semiconductor layer 180 increases. In other words, when the pressing force by which common substrate 150 is pressed increases, the amount of current flowing between upper electrode 171 and semiconductor layer 180 also increases sharply.

Therefore, control unit 105 shown in FIG. 58 can easily sense changes in the amount of current between source line 111 to which TFT element for selection 116 is connected and source line 111 to which pressure sensor 190 is connected, and can accurately calculate the pressure applied to common substrate 150.

A method for manufacturing liquid crystal display device 100 according to the sixth embodiment will be described with reference to FIGS. 64 to 74.

In liquid crystal display device 100 according to the sixth embodiment as well, liquid crystal display device 100 is formed by independently forming TFT array substrate 130 and common substrate 150, and arranging formed TFT array substrate 130 and common substrate 150 to face each other.

FIG. 64 is a cross-sectional view showing a first step of a process of manufacturing TFT array substrate 130. In this FIG. 64, glass substrate 140 having the main surface is prepared. Then, the SiNO layer having a thickness of, for example, approximately 50 nm is formed by plasma enhanced CVD. Then, the SiO₂ layer having a thickness of, for example, approximately 110 nm is formed on the SiNO layer. Underlying layer 131 is thus formed on the main surface of glass substrate 140.

FIG. 65 is a cross-sectional view showing a second step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 65, and Si layer having a thickness of, for example, approximately 50 nm is formed on the upper surface of underlying layer 131 by the plasma enhanced CVD.

Thereafter, the continuous grain silicon layer is formed by irradiation with XeCl excimer laser, and then, this continuous grain silicon layer is patterned by photolithography and the like to form semiconductor layer 132 and semiconductor layer 180.

FIG. 66 is a cross-sectional view showing a third step of the process of manufacturing TFT array substrate 130. In this FIG. 66, the SiO₂ layer having a thickness of, for example, approximately 80 nm is formed by the plasma enhanced CVD to cover semiconductor layer 132 and semiconductor layer 180.

FIG. 67 is a cross-sectional view showing a fourth step of the process of manufacturing TFT array substrate 130. In this FIG. 67, P+ (phosphorus ion) is doped into semiconductor layer 132 and semiconductor layer 180 under the conditions of 45 KV and 5E15 cm⁻².

FIG. 68 is a cross-sectional view showing a fifth step of the process of manufacturing TFT array substrate 130. In this FIG. 68, stacked metal layers 222 are formed on the upper surface of gate insulating layer 133 by sputtering and the like. Specifically, the tungsten (W) layer having a thickness of, for example, approximately 370 nm is formed by sputtering. After the formation of the tungsten layer, the tantalum nitride (TaN) layer having a thickness of for example, approximately 50 nm is formed.

FIG. 69 is a cross-sectional view showing a sixth step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 69, stacked metal layers 222 shown in FIG. 68 is patterned to form gate electrode 134 and upper electrode 171. At least one or more holes 173 are formed in upper electrode 171.

Specifically, as shown in FIG. 62 above, a plurality of holes 173 are formed. Upper electrode 171 is formed to have a square shape and one side thereof has a length of 30 μm. Hole 173 is also formed to have a square shape and one side thereof has a length of 2 μm. spacing between holes 173 is set to be 2 μm.

FIG. 70 is a cross-sectional view showing a seventh step of the process of manufacturing TFT array substrate 130. In this FIG. 70, the resist is first formed and this resist is patterned. Resist pattern 223 is thus formed. This resist pattern 223 has a hole to expose hole 173 to the outside.

Then, the substrate having resist pattern 223 is immersed in buffered hydrogen fluoride (BHF). A mixture obtained by mixing hydrofluoric acid (HF) and ammonium fluoride (NH₄F) at a ratio of 1:10 is used as the buffered hydrogen fluoride (BHF). The substrate is immersed for approximately 13 minutes, for example.

As a result, the buffered hydrogen fluoride that has flown in through hole 173 etches a part of gate insulating layer 133. Consequently, recess 147 is formed under upper electrode 171.

FIG. 71 is a cross-sectional view showing an eighth step of the process of manufacturing TFT array substrate 130. In this FIG. 71, resist pattern 223 is removed, and thereafter, interlayer dielectric 135 is formed on gate insulating layer 133.

Specifically, the silicon oxide layer (SiO₂ layer) having a thickness of approximately 700 nm is formed by the plasma enhanced CVD, and the silicon nitride layer (SiN layer) having a thickness of, for example, approximately 250 nm is formed on this silicon oxide layer. Interlayer dielectric 135 is thus formed.

FIG. 72 is a cross-sectional view showing a ninth step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 72, interlayer dielectric 135 is patterned to form a plurality of contact holes.

FIG. 73 is a cross-sectional view showing a tenth step of the process of manufacturing TFT array substrate 130. In this FIG. 73, a titanium (Ti) layer having a thickness of, for example, approximately 100 nm is first formed. An Al—Si layer having a thickness of, for example, approximately 600 nm is formed on this titanium layer. A titanium (Ti) layer having a thickness of, for example, approximately 200 nm is formed on this Al—Si layer.

After the formation of the stacked metal layers in such a manner, these stacked metal layers are patterned to form drain pad 210, drain electrode 137, source line 111, source electrode 138, contact 146, and connection wiring 124.

FIG. 74 is a cross-sectional view showing an eleventh step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 74, upper insulating layer 136 is formed to cover drain pad 210, drain electrode 137, source line 111, source electrode 138, contact 146, connection wiring 124 and the like. Specifically, the silicon nitride layer (SiN layer) having a thickness of, for example, approximately 200 nm is formed by the plasma enhanced CVD.

Thereafter, upper insulating layer 136 is patterned to form the ITO layer on the upper surface of patterned upper insulating layer 136. This ITO layer is patterned to form pixel electrode 114 shown in FIG. 59. TFT array substrate 130 is thus formed.

In order to form common substrate 150, glass substrate 156 is first prepared. Color filter substrate 151 is formed on the main surface of this glass substrate 156. The ITO layer is formed on the upper surface of this color filter substrate 151 to form common electrode 152.

Thereafter, the acrylic resin layer is formed on the upper surface of this common electrode 152 and this acrylic resin layer is patterned to form pressing member 145. Common substrate 150 shown in FIG. 59 is thus formed.

After the formation of TFT array substrate 130 and common substrate 150 in such a manner, the liquid crystal layer is applied onto the main surface of TFT array substrate 130.

Thereafter, common substrate 150 is arranged above TFT array substrate 130, and TFT array substrate 130 and common substrate 150 are assembled together. Liquid crystal display device 100 shown in FIGS. 59 and 60 is thus formed.

In liquid crystal display device 100 thus configured, the pressing force is applied from the TFT array substrate 130 side.

Consequently, at 0.2 N, control unit 105 can sense a current flowing between source line 111 to which TFT element for selection 116 is connected and source line 111 to which pressure sensor 190 is connected. Furthermore, when the pressing force of approximately 1 N is applied to TFT array substrate 130, a resistance value is reduced to one-eighth.

Seventh Embodiment

A pressure sensor, liquid crystal display device 100 and a method for manufacturing liquid crystal display device 100 according to a seventh embodiment of the present invention will be described with reference to FIGS. 75 to 81 and FIG. 58. The same reference characters are given to the components shown in FIGS. 75 to 81 that are the same as or corresponding to those shown in FIGS. 1 to 74 above, and description thereof will not be repeated.

An electrical circuit of liquid crystal display device 100 according to the seventh embodiment corresponds to the electrical circuit shown in FIG. 58.

FIG. 75 is a cross-sectional view of liquid crystal display device 100 according to the seventh embodiment and is a cross-sectional view showing TFT element 115. FIG. 76 is a cross-sectional view of liquid crystal display device 100 according to the seventh embodiment and is a cross-sectional view showing pressure sensor 190.

As shown in these FIGS. 75 and 76, TFT array substrate 130 includes glass substrate 140, underlying layer 141 formed on the main surface of glass substrate 140, and TFT element 115 and pressure sensor 190 formed on this underlying layer 141.

TFT element 115 is formed on the upper surface of underlying layer 131 formed on underlying layer 141. TFT element 115 includes semiconductor layer 132 formed on underlying layer 131, gate electrode 134 formed on the upper surface of underlying layer 131 to cover semiconductor layer 132, and drain electrode 137 and source electrode 138 connected to semiconductor layer 132.

Interlayer dielectric 135 is formed on gate insulating layer 133 to cover gate electrode 134. Drain pad 210 and source line 111 are formed on the upper surface of interlayer dielectric 135. Drain electrode 137 is connected to drain pad 210, and source electrode 138 is connected to source line 111.

In FIG. 76, pressure sensor 190 includes lower electrode 172 formed on underlying layer 141, and lower electrode 172 located on the common substrate 150 side with respect to this lower electrode 172 and arranged to face lower electrode 172.

Underlying layer 131 and gate insulating layer 133 are formed on the upper surface of lower electrode 172. Recess 147 is formed between lower electrode 172 and upper electrode 171. Recess 147 is defined by a hole formed in underlying layer 131 and the hole formed in gate insulating layer 133, and the upper surface of lower electrode 172 is located at the bottom of this recess 147.

Therefore, in liquid crystal display device 100 according to the seventh embodiment as well, upper electrode 171 can deform to deflect to go into recess 147.

Therefore, in liquid crystal display device 100 according to the seventh embodiment as well, when common substrate 150 is pressed, upper electrode 171 comes into contact with lower electrode 172, and a current flows between upper electrode 171 and lower electrode 172.

When the pressing force by which common substrate 150 is pressed increases, a contact area between upper electrode 171 and lower electrode 172 increases, and the current flowing between upper electrode 171 and lower electrode 172 increases. As a result, control unit 105 shown in FIG. 58 can sense the pressing force applied to common substrate 150.

A method for manufacturing liquid crystal display device 100 according to the seventh embodiment will be described with reference to FIGS. 77 to 80.

In liquid crystal display device 100 according to the seventh embodiment as well, liquid crystal display device 100 is formed by separately forming TFT array substrate 130 and common substrate 150, and assembling formed common substrate 150 and TFT array substrate 130 together.

FIG. 77 is a cross-sectional view showing a first step of a process of manufacturing TFT array substrate 130. As shown in this FIG. 77, glass substrate 140 having the main surface is prepared. Underlying layer 141 is formed on the main surface of this glass substrate 140. Underlying layer 141 is made of, for example, SiO₂, SiN, SiNO and the like. Underlying layer 141 has a film thickness of, for example, 500 nm or less, and preferably 400 nm or less.

The metal layer made of molybdenum (Mo), tungsten (W) and the like is formed on the upper surface of this underlying layer 141 by sputtering. Then, this metal layer is patterned to form lower electrode 172. Lower electrode 172 is formed to have a film thickness of, for example, 50 nm or more and 600 nm or less. Lower electrode 172 is preferably formed to have a film thickness of 50 nm or more and 300 nm or less.

The insulating layer such as a SiO₂ layer, a SiN layer and a SiNO layer is formed to cover lower electrode 172, and underlying layer 131 is formed.

FIG. 78 is a cross-sectional view showing a second step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 78, the amorphous semiconductor layer is deposited on underlying layer 131. The amorphous semiconductor layer has a film thickness of, for example, 20 nm or more and 200 nm or less. The amorphous semiconductor layer preferably has a film thickness of approximately 30 nm or more and 70 nm. Thereafter, this amorphous semiconductor layer is crystallized to form the continuous grain silicon layer. The continuous grain silicon layer is patterned to form semiconductor layer 132.

The insulating layer made of SiO₂, SiN, SiNO and the like is formed, and gate insulating layer 133 is formed. Gate insulating layer 133 has a film thickness of, for example, 20 nm or more and 200 nm or less, and preferably 50 nm or more and 120 nm or less.

Then, the metal layer is formed on the upper surface of gate insulating layer 133. This metal layer is formed of, for example, a metal film made of tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or an alloy film containing tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo) and the like, or a compound containing an element such as tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo).

This metal layer has a film thickness of for example, 50 nm or more and 600 nm or less, and preferably 100 nm or more and 500 nm or less.

Thereafter, this metal layer is patterned to form gate electrode 134 and upper electrode 171. At this time, hole 173 is simultaneously formed in upper electrode 171. As described above, in the seventh embodiment as well, upper electrode 171 and gate electrode 134 can be formed in the same step.

FIG. 79 is a cross-sectional view showing a third step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 79, the resist is first formed and this resist is patterned. Resist pattern 223 is thus foamed. This resist pattern 223 has a hole to expose hole 173 to the outside.

Then, the substrate is immersed in an acid-based solution such as an HF (hydrogen fluoride) aqueous solution. The solution flows in through hole 173 and etches gate insulating layer 133 and underlying layer 131. As a result, recess 147 is formed.

FIG. 80 is a cross-sectional view showing a fourth step of the process of manufacturing TFT array substrate 130. As shown in this FIG. 80, resist pattern 223 shown in FIG. 79 is removed. Interlayer dielectric 135 is formed. This interlayer dielectric 135 is patterned to form a plurality of contact holes. Thereafter, the metal layer is formed on the upper surface of interlayer dielectric 135 and this metal layer is patterned to form drain pad 210, drain electrode 137, source electrode 138, source line 111, contact 146, and connection wiring 124.

Thereafter, upper insulating layer 136 is formed and this upper insulating layer 136 is patterned to form the contact hole.

The ITO layer is formed on the upper surface of upper insulating layer 136 having this contact hole and this ITO layer is patterned to form pixel electrode 114. TFT array substrate 130 is thus formed.

Common substrate 150 is formed similarly to common substrate 150 of liquid crystal display device 100 according to the third embodiment described above.

Common substrate 150 and TFT array substrate 130 thus formed are assembled together. Liquid crystal display device 100 according to the seventh embodiment is thus formed.

FIG. 81 is a cross-sectional view showing a modification of liquid crystal display device 100 according to the seventh embodiment. As shown in this FIG. 81, light blocking layer 148 may be formed on underlying layer 141 located below semiconductor layer 132.

Light blocking layer 148 is made of a metal of the same kind as that of lower electrode 172, and a film thickness of light blocking layer 148 is substantially identical to a film thickness of lower electrode 172.

Light blocking layer 148 and lower electrode 172 are formed by patterning one metal layer and can be formed in the same patterning step.

Although the example in which the present invention is applied to the liquid crystal display device has been described in the aforementioned first to seventh embodiments, the present invention is also applicable to an organic electroluminescence (EL) display or a plasma display. In addition, each substrate may be a flexible substrate. When the present invention is applied to the organic electroluminescence display, an organic EL layer serves as the display medium layer.

This organic electroluminescence display includes a first substrate formed on a first main surface, a second substrate spaced apart from the first substrate and having a second electrode on a main surface facing the first main surface, and an organic EL layer formed between a first electrode and the second electrode.

The organic electroluminescence display further includes a lower electrode formed on the first substrate, an upper electrode arranged closer to the second substrate than this lower electrode, and a sensing unit capable of sensing a capacitance between the lower electrode and the upper electrode or an amount of current flowing between the lower electrode and the upper electrode. At least one of the upper electrode and the lower electrode can deform to conform to the other.

When the present invention is applied to the plasma display, a phosphor layer serves as the display medium layer. This plasma display includes a front plate and a back plate. The front plate includes a front glass substrate, a display electrode formed on a lower surface of this front glass substrate, a light blocking layer, and a dielectric layer formed on the lower surface of the front glass substrate to cover the display electrode and the light blocking layer. A protection layer is formed on a lower surface of this dielectric layer.

The back plate includes a back glass substrate, an address electrode formed on an upper surface of this back glass substrate, an underlying dielectric layer formed on the upper surface of the back glass substrate to cover this address electrode, a plurality of partition walls formed on this underlying dielectric layer and partitioning a discharge space, and a phosphor layer formed in a groove between the partition walls. The front plate and the back plate are arranged to face each other. A perimeter is hermetically sealed by a sealant, and a discharge gas is injected into the discharge space.

This plasma display further includes a lower electrode arranged on the back plate side, an upper electrode arranged on the back plate side, and a sensing unit capable of sensing a capacitance or an amount of current defined by the upper electrode and the lower electrode. At least one of the upper electrode and the lower electrode can deform to conform to the other.

Eighth Embodiment

A pressure detecting device according to an eighth embodiment based on the present invention will be described with reference to FIGS. 82 and 83. As shown in FIG. 82, a pressure sensor 118 as a pressure detecting device includes a glass substrate 140 as a substrate, a lower electrode 172 arranged on glass substrate 140, an upper electrode 171 spaced apart from lower electrode 172 and facing lower electrode 172, the upper electrode having a hole 173 as one or more through-openings, and a source line 111 as a change extracting wiring for detecting a change in electrical state caused by upper electrode 171 receiving pressure to deflect toward lower electrode 172.

When pressure is applied, this pressure sensor 118 deforms as shown in FIG. 83.

In the pressure detecting device according to the present embodiment, since the upper electrode facing the lower electrode has one or more through-openings, a gap can efficiently be formed by distributing an etching solution via this through-openings at the time of manufacture.

Although FIGS. 82 and 83 present only one hole as a through-opening, it is preferable that two or more holes be provided practically, as shown in FIGS. 30 to 33. It is more preferable that a large number of holes be provided. In the case of providing a large number of holes, arrangement in a matrix form as shown in FIG. 31 allows a large number of holes to be efficiently arranged in a region of limited area, which is more preferable.

Similarly to the pressure sensor described in the third embodiment with reference to FIGS. 27 to 33, when a pressure is applied, the pressure detecting device according to the present embodiment can also detect the pressure by a sharp change in capacitance between upper electrode 171 and lower electrode 172.

Although the present embodiment has described the structure in which the gap formed between upper electrode 171 and lower electrode 172 communicates with liquid crystal layer 160 and liquid crystals enter the gap, the structure may be such that the gap does not communicate with liquid crystal layer 160 as shown in FIGS. 28 and 29.

The third embodiment and the present embodiment present a structure in which lower electrode 172 is not directly exposed to the gap but lower electrode 172 is covered with underlying layer 131. That is, underlying layer 131 as an insulating film preferably covers a surface of lower electrode 172 facing upper electrode 171. The upper electrode and the lower electrode can then be prevented from being short-circuited undesirably.

However, the present invention is not limited to the structure in which lower electrode 172 is covered with a certain insulating film. As shown in FIG. 61, the lower electrode may be directly exposed to the gap. Conversely, it may be configured such that the upper surface of lower electrode 172 is exposed and the lower surface of the upper electrode is covered with an insulating film. In that case, however, the through-opening passes through this insulating film to cause the gap and liquid crystal layer 160 to communicate with each other. That is, in other words, it is preferable that the insulating film cover a surface of upper electrode 171 facing lower electrode 172 and the through-opening be provided to extend through upper electrode 171 and the insulating film together. By adopting this structure, the etching solution can be distributed via the through-opening, and the gap can be formed efficiently.

Although the lower electrode is semiconductor layer 180 in FIG. 61, the lower electrode may be formed of metal. The lower electrode may be formed of metal such as Mo, for example. In that case, a structure shown in FIG. 84 is conceivable. Although underlying layer 141 is present between lower electrode 172 and glass substrate 140 in FIG. 84, underlying layer 141 is not essential considering the application of the present invention.

FIG. 84 shows the structure in which underlying layer 131 partially extends over underlying electrode 172 and a large opening is formed on the upper surface of underlying electrode 172. As a result, a portion of the upper surface of lower electrode 172 is directly exposed to the gap. Instead of adopting such a structure, it may be configured such that underlying layer 131 completely covers the upper surface of lower electrode 172. In that case, since underlying layer 131 will be present between the upper electrode and the lower electrode, the dielectric constant can be increased. A pressure detecting device of high sensitivity can thus be obtained.

In FIG. 84, lower electrode 172 may have a double layer structure in which Al (aluminum) and W (tungsten) are stacked sequentially away from glass substrate 140. That is, it may be configured such that an Al layer 71 is formed on glass substrate 140 and a W layer 72 is formed thereon, as pressure sensor 118 shown in FIG. 85. The combination of Al layer 71 and W layer 72 serves as lower electrode 172. With such a structure, W layer 72 plays the role of an etching stopper layer when the sacrificial layer is etched for forming a gap, which can prevent the lower electrode from being overetched. Favorable etching can thus be achieved.

In FIGS. 82 and 85, gate insulating layer 133 is located above the gap, and the through-opening is provided to extend through upper electrode 171 and gate insulating layer 133. However, it is not essential that gate insulating layer 133 be located at this position considering the application of the present invention. The lower surface of upper electrode 171 may be directly exposed to the gap.

Although upper electrode 171 shall be formed of metal in the above description as described in the third embodiment, upper electrode 171 is not necessarily made of metal. Upper electrode 171 may be formed of a silicon thin film doped with impurities. By adopting this structure, an existing silicon thin film can be utilized without adding a step of forming of a new metal film in the manufacture of a display device or the like.

Ninth Embodiment

A pressure detecting device according to a ninth embodiment based on the present invention will be described with reference to FIGS. 86 and 87. As shown in FIG. 86, in pressure sensor 118 as the pressure detecting device according to the present embodiment, a space filled with an organic material 61 is located between lower electrode 172 and upper electrode 171. For example, polyimide resin is used as organic material 61. Organic material 61 may be injected in the liquid state via hole 173 of upper electrode 171 as one or more through-openings, and then solidified.

In the example shown in FIG. 86, organic material 61 as a filling reaches the vicinity of the upper end of hole 173 of upper electrode 171. Considering the application of the present invention, it may be configured such that organic material 61 as a filling completely fills hole 173, or partway fills hole 173, or fills merely a portion below the lower end of hole 173.

Although the example shown in FIG. 86 presents a structure in which upper electrode 171 and lower electrode 172 are directly exposed to the gap and organic material 61 is in direct contact with both upper electrode 171 and lower electrode 172, the form of application of the present invention is not limited to this. It may be a structure as shown in FIG. 87, for example. In pressure sensor 118 shown in FIG. 87, gate insulating layer 133 covers the lower surface of upper electrode 171, and underlying layer 131 as an insulating layer covers the upper surface of lower electrode 172. In this example, directly exposed to the gap are gate insulating layer 133 and underlying layer 131. Such a structure may be adopted, and the gap may be filled with organic material 61. Organic material 61 in this case may also be polyimide resin.

In FIG. 87, both the insulating layer covering the lower surface of upper electrode 171 and the insulating layer covering the upper surface of lower electrode 172 are present, however, it may be configured such that either of these two insulating layers is absent considering the application of the present invention.

To manufacture the pressure detecting device according to the present embodiment, a step of applying a polyamic acid solution after forming upper electrode 171 having hole 173, drying, and then performing heat treatment at 450° C. may be performed in the manufacturing method described in the third, sixth or seventh embodiment. A structure in which the gap formed between upper electrode 171 and lower electrode 172 is filled with polyimide resin as organic material 61 is thus obtained.

Even in the structure in which upper electrode 171 and lower electrode 172 are both directly exposed to the gap or the structure in which the surface of one or both of upper electrode 171 and lower electrode 172 is covered with an insulating film as seen from the inside of the gap, the structure filled with organic material 61 can be obtained similarly by applying a liquid such as a polyamic acid solution, drying and heat treating.

With the pressure detecting device according to the present embodiment, the gap is filled with the organic material, and the rigidity can thus be enhanced entirely. Moreover, in the system of detecting pressure by means of capacitance, the dielectric constant ∈ can be increased by selecting the type of organic material with which the gap is filled. The sensitivity in pressure detection can thus be enhanced.

Tests conducted by the inventors have revealed that, in the case of the structure in which the gap was filled with the organic material as shown in the present embodiment, sensitivity was about 3 times that of the structure in which the gap was not filled with an organic material. Herein, “sensitivity” refers to the amount of change in electrostatic capacitance with respect to the amount of depression. The pressure detecting device of high sensitivity could thus be obtained.

(TFT Substrate with Pressure Detecting Device)

A TFT substrate with a pressure detecting device according to the present invention includes a substrate, a thin film transistor (hereinafter called “TFT”) arranged on the substrate, and the pressure detecting device according to any one of the embodiments described so far. The TFT has a gate electrode, and the upper electrode is formed of the same layer as the gate electrode. As described above, the structure in which the upper electrode is formed of the same layer as the gate electrode of TFT is preferable because it can prevent the number of steps from increasing while enjoying the advantage that the etching solution can be distributed via the through-opening to form the gap efficiently.

Tenth Embodiment

FIG. 88 shows a flowchart of a method for manufacturing a pressure detecting device according to a tenth embodiment based on the present invention. This method for manufacturing a pressure detecting device includes a step S1 of forming a lower electrode on a substrate, a step S2 of forming a sacrificial layer on the lower electrode, a step S3 of forming an upper electrode having one or more through-openings on the sacrificial layer, a step S4 of etching the sacrificial layer via the one or more through-openings, thereby forming a gap between the upper electrode and the lower electrode, and a step S5 of forming a detecting unit for detecting a change in electric signal caused by the upper electrode receiving pressure to deflect toward the lower electrode. Steps S1 to S5 herein can be read in the manufacturing method described with reference to FIGS. 64 to 74 in the sixth embodiment. Step S1 is a step of forming semiconductor layer 180 as a lower electrode on glass substrate 140 as shown in FIG. 65, for example. The lower electrode may be formed immediately above and in contact with the substrate, or may be formed above the substrate with any other layer interposed therebetween as shown in FIG. 65. Step S2 is a step of forming gate insulating layer 133 playing the role of a sacrificial layer on semiconductor layer 180 as a lower electrode as shown in FIGS. 66 and 67, for example. Step S3 is a step of forming upper electrode 171 having hole 173 as one or more through-openings on gate insulating layer 133 as shown in FIGS. 68 and 69, for example. In FIG. 69, hole 173 is drawn only at one position for ease of description, however, it may practically be formed at a plurality of positions. Step S4 is a step of forming a gap by etching the sacrificial layer as shown in FIG. 70, for example. In the example shown in FIG. 70, recess 147 is formed via hole 173 of upper electrode 171. Step S5 is a step of forming contact holes in interlayer dielectric 135 to form a metal layer, thereby forming source line 111, contact 146 and connection wiring 124, as shown in FIGS. 72 and 73, for example.

By the method for manufacturing the pressure detecting device according to the present embodiment, since one or more through-openings are formed in the upper electrode facing the lower electrode, the etching solution can be distributed via these through-openings, so that the gap can be formed efficiently.

A preferable form of the method for manufacturing the pressure detecting device according to the present embodiment is as follows: Although gate insulating layer 133 made of SiO₂ plays the role of the sacrificial layer in the above-described examples, it is also considered to use a Si layer as the sacrificial layer. An insulating underlying layer which will be mentioned below may be formed of SiO₂, for example.

Preferably, a step of forming an insulating underlying layer on the substrate to cover the lower electrode is included before step S2 of forming the sacrificial layer, and in the step of forming the gap, at least a portion of the underlying layer is left to cover the surface of the lower electrode exposed to the gap. In such a manufacturing method, the lower electrode will be covered with an insulating film without being directly exposed to the inside of the gap. When the sacrificial layer is made of Si and the underlying layer is made of SiO₂, for example, Si alone can be removed leaving SiO₂ in the step of forming the gap, and the underlying layer can thus be left in this manner. Specifics are as shown in FIG. 89. Underlying layer 131 covers the upper side of lower electrode 172. The gap is formed by removing, by etching, most of semiconductor layer 180 as a sacrificial layer provided on underlying layer 131. Etching is performed via holes 173 and 174. In the structure thus obtained, the insulating underlying layer will be present between the upper electrode and the lower electrode, so that the dielectric constant can be increased. A pressure detecting device of high sensitivity can thus be obtained.

Although gate insulating layer 133 is arranged above sacrificial layer 180 and under upper electrode 171 in the example shown in FIG. 89, gate insulating layer 133 may be absent at this position. However, since it is preferable to form an insulating film to cover the sacrificial layer as will be described below, gate insulating layer 133 made of SiO₂ is utilized for use as an insulating film in the example shown in FIG. 89.

That is, preferably, a step of forming an insulating film to cover the sacrificial layer is included before Step S3 of forming the upper electrode, and a step of leaving at least a portion of the insulating film on the sacrificial layer and under the upper electrode and providing a through-opening in the insulating film to communicate with the one or more through-openings of the upper electrode is included before the step of forming the gap. Etching in the step of forming the gap is preferably performed via the one or more through-openings that cause the upper electrode and the insulating film to communicate with each other. When the sacrificial layer is made of Si and the insulating layer covering the sacrificial layer is made of SiO₂, the insulating film can also be left by providing the through-openings in this manner and performing etching for removing the sacrificial layer via the through-openings. In the example shown in FIG. 89, at least a portion of gate insulating layer 133 made of SiO₂ is left as an insulating film above sacrificial layer 180 and under upper electrode 171. In such a manufacturing method, the upper electrode will not be exposed directly to the gap, but will be covered with the insulating film. The structure thus obtained can prevent the upper electrode and the lower electrode from short-circuiting undesirably.

Although lower electrode 172 has a double layer structure including Al layer 71 and W layer 72 in the example shown in FIG. 89, lower electrode 172 may be a single layer structure mainly made of Mo.

Preferably, the method for manufacturing the pressure detecting device includes a step of providing an etching stopper layer on the lower electrode, and etching in the step of forming the gap is performed while restraining the etching range utilizing the etching stopper layer. The “etching range” as used herein may be a two-dimensional range, or may be a range in the thickness direction. In etching of semiconductor layer 180 performed from FIGS. 35 to 36, for example, underlying layer 131 provided on lower electrode 172 plays the role of the etching stopper layer, which prevents etching from progressing further downwardly.

Preferably, the step of forming a silicon layer as a portion of a thin film transistor also serves as step S3 of forming the upper electrode. In such a manufacturing method, the effects of the present invention can be obtained while preventing the number of steps from increasing.

Preferably, the step of forming a gate insulating film as a portion of the thin film transistor also serves as step S2 of forming the sacrificial layer. In such a manufacturing method, the effects of the present invention can be obtained while preventing the number of steps from increasing.

Preferably, the method for manufacturing the pressure detecting device includes the steps of forming a silicon layer and locally doping the silicon layer with impurities to cause a difference in etching rate, and a portion of the silicon layer is turned into the sacrificial layer utilizing the difference in etching rate. In such a manufacturing method, a portion of the silicon layer is removed as the sacrificial layer, while the remaining portion of the silicon layer can be left.

Preferably, the portion of the silicon layer is turned into the sacrificial layer by doping a peripheral portion with the impurities while avoiding a central portion of a region where the pressure detecting device is to be formed. The peripheral portion of the silicon layer is changed in character to be less likely to be removed during etching by being doped with the impurities, and the central portion is changed in character to be likely to be removed during etching by not being doped with the impurities. By providing such a difference, the central portion of the silicon layer can be removed as the sacrificial layer, and the gap can be formed in a manner limited to a desired region.

The present invention is also directed to a display device and a method for manufacturing the display device. In a first aspect, the display device according to the present invention includes any one of the above-described pressure detecting devices. In a second aspect, the display device according to the present invention includes a TFT substrate with a pressure detecting device. The method for manufacturing the display device according to the present invention includes each step of the method for manufacturing any one of the above-described pressure detecting devices. In such a structure, the gap can be formed efficiently, and a favorable pressure detecting device can be formed. A display device including favorable pressure detecting means can thus be obtained.

It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the claims not by the description above, and is intended to include any modification within the meaning and scope equivalent to the terms of the claims.

INDUSTRIAL APPLICABILITY

The present invention is applicable to a pressure detecting device and a method for manufacturing the same, a display device and a method for manufacturing the same, and a TFT substrate with a pressure detecting device.

REFERENCE SIGNS LIST

-   -   61 organic material; 71 Al layer; 72 W layer; 100 liquid crystal         display device; 101 source driver; 102 gate driver; 103 sensor         driver; 105 control unit; 110 pixel; 111 source line; 112 gate         line; 113 gate line for sensing; 114 pixel electrode; 115 TFT         element; 116 TFT element for selection; 117 output element; 118,         190 pressure sensor; 120 pressure sensing element; 121, 138,         183, 203 source electrode; 122 gate electrode; 123 semiconductor         layer; 124 connection wiring; 125, 137, 182, 202 drain         electrode; 130 TFT array substrate; 131 underlying layer; 132,         180, 200 semiconductor layer; 133 gate insulating layer; 134,         181, 201 gate electrode; 135, 139 interlayer dielectric; 136         upper insulating layer; 140 glass substrate; 141 underlying         layer; 145 pressing member; 146 contact; 147 recess; 148 light         blocking layer; 149 resin layer; 150 common substrate; 151 color         filter substrate; 152 common electrode; 153 colored layer; 155         black matrix; 156 glass substrate; 157 plastic resin layer; 158         resin pattern; 160 liquid crystal layer; 161 spacer; 170         projection; 171 upper electrode; 172, 189, 191, 218 lower         electrode; 173, 174 hole; 184 contact; 185 pad unit; 186         connection unit; 187 reflection electrode; 210 drain pad; 211         wiring; 212 transparent conductive layer; 213 electrode unit;         214 wiring; 215 transparent conductive layer; 216 projection;         217 conductive layer; 219 pad unit; 220 recess; 221 projection;         222 stacked metal layers; 223 resist pattern 

1. A pressure detecting device comprising: a substrate; a lower electrode arranged on said substrate; an upper electrode spaced apart from said lower electrode and facing said lower electrode, said upper electrode having one or more through-openings; and a change extracting wiring for detecting a change in electrical state caused by said upper electrode receiving pressure to deflect toward said lower electrode.
 2. The pressure detecting device according to claim 1, wherein an insulating film covers a surface of said lower electrode facing said upper electrode.
 3. The pressure detecting device according to claim 1, wherein an insulating film covers a surface of said upper electrode facing said lower electrode, and said through-openings are provided to extend through said upper electrode and said insulating film together.
 4. The pressure detecting device according to claim 1, wherein said upper electrode is a silicon thin film doped with an impurity.
 5. The pressure detecting device according to claim 1, wherein a space filled with an organic material is located between said lower electrode and said upper electrode.
 6. A TFT substrate with a pressure detecting device, comprising: said substrate; a thin film transistor arranged on said substrate; and the pressure detecting device as defined in claim 1, wherein said thin film transistor includes a gate electrode, and said upper electrode is made of the same layer as said gate electrode.
 7. A method for manufacturing a pressure detecting device, comprising the steps of: forming a lower electrode on a substrate; forming a sacrificial layer on said lower electrode; forming an upper electrode having one or more through-openings on said sacrificial layer; etching said sacrificial layer via said one or more through-openings to form a gap between said upper electrode and said lower electrode; and forming a detecting unit for detecting a change in electrical signal caused by said upper electrode receiving pressure to deflect toward said lower electrode.
 8. The method for manufacturing a pressure detecting device according to claim 7, comprising the step of forming an insulating underlying layer on said substrate to cover said lower electrode before the step of forming said sacrificial layer, wherein in the step of forming said gap, at least a portion of said underlying layer is left to cover a surface of said lower electrode exposed to said gap.
 9. The method for manufacturing a pressure detecting device according to claim 7, comprising the steps of: forming an insulating film to cover said sacrificial layer before the step of forming said upper electrode; and before the step of forming said gap, leaving at least a portion of said insulating film on said sacrificial layer and under said upper electrode and providing a through-opening in said insulating film to communicate with said one or more through-openings in said upper electrode, wherein etching in the step of forming said gap is performed via said one or more through-openings that cause said upper electrode and said insulating film to communicate with each other.
 10. The method for manufacturing a pressure detecting device according to claim 7, comprising the step of: providing an etching stopper layer on said lower electrode, wherein etching in the step of forming said gap is performed while restraining an etching range utilizing said etching stopper layer.
 11. The method for manufacturing a pressure detecting device according to claim 7, wherein the step of forming a silicon layer as a portion of a thin film transistor also serves as the step of forming said upper electrode.
 12. The method for manufacturing a pressure detecting device according to claim 7, wherein the step of forming a gate insulating film as a portion of the thin film transistor also serves as the step of forming said sacrificial layer.
 13. The method for manufacturing a pressure detecting device according to claim 7, comprising the steps of: forming a silicon layer; and locally doping said silicon layer with an impurity to cause a difference in etching rate, wherein a portion of said silicon layer is turned into said sacrificial layer utilizing said difference in etching rate.
 14. The method for manufacturing a pressure detecting device according to claim 13, wherein the portion of said silicon layer is turned into said sacrificial layer by doping a peripheral portion with said impurity while avoiding a central portion of a region where the pressure detecting device is to be formed.
 15. A display device comprising the pressure detecting device as defined in claim
 1. 16. A display device comprising the TFT substrate with a pressure detecting device as defined in claim
 6. 17. A method for manufacturing a display device, comprising each step of the method for manufacturing the pressure detecting device as defined in claim
 7. 